Interrupt Priority Registers A To C, E To H, K, And L (Ipra To Iprc, Ipre To Iprh, Iprk, And Iprl) - Renesas H8SX/1650 Hardware Manual

Section 5 Interrupt Controller
Bit Bit Name
2 CPUP2
1 CPUP1
0 CPUP0
Note: When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
*
cannot be modified.
5.3.3 Interrupt Priority Registers A to C, E to H, K, and L (IPRA to IPRC, IPRE to
IPRH, IPRK, and IPRL)
IPR sets priory (levels 7 to 0) for interrupts other than NMI.
Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,
and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between
the interrupt sources and the IPR settings, see table 5.2.
Bit 15

Bit Name
Initial Value 0
R/W R
Bit 7

Bit Name
Initial Value 0
R/W R
Rev.2.00 Jun. 28, 2007 Page 90 of 666
REJ09B0311-0200
Initial
Value R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
14 13
IPR14 IPR13
1 1
R/W R/W
6 5
IPR6 IPR5
1 1
R/W R/W
Description
CPU Priority Level 2 to 0
These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
becomes valid and the priority of CPU processing is
assigned in accordance with the settings of bits CPUP2
to CPUP0.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
12 11

IPR12
1 0
R/W R
4 3

IPR4
1 0
R/W R
10 9
IPR10 IPR9
1 1
R/W R/W
2 1
IPR2 IPR1
1 1
R/W R/W
8
IPR8
1
R/W
0
IPR0
1
R/W