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5.3.2
Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0
sets the priority of the corresponding interrupt.
Bit
Bit Name
15
14
IPR14
13
IPR13
12
IPR12
11
10
IPR10
9
IPR9
8
IPR8
7
Initial Value R/W
0
1
R/W
1
R/W
1
R/W
0
1
R/W
1
R/W
1
R/W
0
Description
Reserved
This bit is always read as 0. Write is invalid.
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Reserved
This bit is always read as 0. Write is invalid.
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Reserved
This bit is always read as 0. Write is invalid.
Rev. 1.00, 09/03, page 69 of 704
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