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ST STM32G4 Series Reference Manual

ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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RM0440

Reference manual

STM32G4 Series

®

advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32G4 Series microcontroller memory and peripherals.

The STM32G4 Series is a family of microcontrollers with different memory sizes, packages

and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

®

®

®

For information on the Arm

Cortex

-M4 core, refer to the Cortex

-M4 Technical Reference

Manual.

Related documents

®

• Cortex

-M4 Technical Reference Manual, available from: http://infocenter.arm.com

• STM32G4xx datasheets

®

• STM32F3, STM32F4, STM32G4 and STM32L4 Series Cortex

-M4 programming manual

(PM0214)

May 2019

RM0440 Rev 1

1/2083

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Summary of Contents for ST STM32G4 Series

Page 1 This reference manual targets application developers. It provides complete information on how to use the STM32G4 Series microcontroller memory and peripherals. The STM32G4 Series is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.
Page 2: Table Of Contents
Contents RM0440 Contents Documentation conventions ....... . . 71 General information ......... 71 List of abbreviations for registers .
Page 3 RM0440 Contents 3.3.2 Error code correction (ECC) ....... . . 93 3.3.3 Read access latency .
Page 4 Contents RM0440 3.7.18 Flash Securable area bank2 register (FLASH_SEC2R) ... 142 3.7.19 FLASH register map ........143 Embedded Flash memory (FLASH) for category 2 devices .
Page 5 RM0440 Contents 4.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER) ..181 4.7.11 Flash WRP area A address register (FLASH_WRP1AR) ..181 4.7.12 Flash WRP area B address register (FLASH_WRP1BR) ..182 4.7.13 Flash Securable area register (FLASH_SEC1R) .
Page 6 Contents RM0440 5.4.8 Power Port A pull-up control register (PWR_PUCRA) ... . . 219 5.4.9 Power Port A pull-down control register (PWR_PDCRA) ..219 5.4.10 Power Port B pull-up control register (PWR_PUCRB) .
Page 7 RM0440 Contents 6.2.15 Clock-out capability ........241 6.2.16 Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17 .
Page 8 Contents RM0440 6.4.28 Control/status register (RCC_CSR) ......288 6.4.29 Clock recovery RC register (RCC_CRRCR) ....290 6.4.30 Peripherals independent clock configuration register (RCC_CCIPR2) 291 6.4.31...
Page 9 RM0440 Contents 8.3.10 Output configuration ........313 8.3.11 Alternate function configuration .
Page 10 Contents RM0440 9.2.7 SYSCFG CCM SRAM control and status register (SYSCFG_SCSR) . 334 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) ... . 335 9.2.9 SYSCFG CCM SRAM write protection register (SYSCFG_SWPR) . . 336 9.2.10 SYSCFG CCM SRAM key register (SYSCFG_SKR) .
Page 11 RM0440 Contents 11.5 DMA interrupts ..........371 11.6 DMA registers .
Page 12 Contents RM0440 Nested vectored interrupt controller (NVIC) ....399 13.1 NVIC main features ........399 13.2 SysTick calibration value register .
Page 13 RM0440 Contents 15.3.2 CRC internal signals ........420 15.3.3 CRC operation .
Page 14 Contents RM0440 17.3.4 Output buffer ..........451 17.3.5 Initialisation functions .
Page 15 RM0440 Contents 18.6.1 External memory interface signals ......518 18.6.2 NAND Flash supported memories and transactions ....520 18.6.3 Timing diagrams for NAND Flash memory .
Page 16 Contents RM0440 19.5.7 QUADSPI address register (QUADSPI_AR) ....556 19.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) ... . 557 19.5.9 QUADSPI data register (QUADSPI_DR) .
Page 17 RM0440 Contents 20.4.22 Programmable resolution (RES) - fast conversion mode ..602 20.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 603 20.4.24 End of conversion sequence (EOS, JEOS) ..... 603 20.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) .
Page 18 Contents RM0440 20.6.22 ADC Calibration Factors (ADC_CALFACT) ..... 673 20.6.23 ADC Gain compensation Register (ADC_GCOMP) ....674 20.7 ADC common registers .
Page 19 RM0440 Contents 21.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) ......... 718 21.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) .
Page 20 Contents RM0440 23.1 COMP introduction ......... 736 23.2 COMP main features .
Page 21 RM0440 Contents 24.5.8 OPAMP2 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) 776 24.5.9 OPAMP3 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) 778 24.5.10 OPAMP4 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) 780 24.5.11 OPAMP5 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) 782 24.5.12 OPAMP6 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) 784 24.5.13 OPAMP register map .
Page 22 Contents RM0440 26.3.2 HRTIM pins and internal signals ......805 26.3.3 Clocks ..........808 26.3.4 Timer A..F timing units .
Page 23 RM0440 Contents 26.5.8 HRTIM master timer compare 1 register (HRTIM_MCMP1R) ..924 26.5.9 HRTIM master timer compare 2 register (HRTIM_MCMP2R) ..925 26.5.10 HRTIM master timer compare 3 register (HRTIM_MCMP3R) ..925 26.5.11 HRTIM master timer compare 4 register (HRTIM_MCMP4R) .
Page 24 Contents RM0440 26.5.41 HRTIM timer B capture 1 control register (HRTIM_CPT1BCR) ..972 26.5.42 HRTIM timer C capture 1 control register (HRTIM_CPT1CCR) ..972 26.5.43 HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) ..973 26.5.44 HRTIM timer E capture 1 control register (HRTIM_CPT1ECR) .
Page 25 RM0440 Contents 26.5.76 HRTIM ADC extended trigger register (HRTIM_ADCER) ..1021 26.5.77 HRTIM ADC trigger update register (HRTIM_ADCUR) ... 1024 26.5.78 HRTIM ADC post scaler register 1 (HRTIM_ADCPS1) ... 1025 26.5.79 HRTIM ADC post scaler register 2 (HRTIM_ADCPS2) .
Page 26 Contents RM0440 27.3.26 Direction bit output ........1120 27.3.27 UIF bit remapping .
Page 27 RM0440 Contents 27.6.22 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8, 20) ..1167 27.6.23 TIMx capture/compare mode register 3 (TIMx_CCMR3)(x = 1, 8, 20) ....... 1168 27.6.24 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8, 20) .
Page 28 Contents RM0440 28.4.21 Timer input XOR function ........1248 28.4.22 Timers and external trigger synchronization .
Page 29 RM0440 Contents 28.5.26 TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) ..1290 28.5.27 TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) ..1291 28.5.28 TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) .
Page 30 Contents RM0440 29.4.26 Timer synchronization (TIM15) ......1343 29.4.27 TIM15/TIM16/TIM17 DMA requests ......1343 29.4.28 Debug mode .
Page 31 RM0440 Contents 29.8.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) ......1380 29.8.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .
Page 32 Contents RM0440 30.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) ..1414 30.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) ....1415 30.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) .
Page 33 RM0440 Contents 31.7.6 LPTIM compare register (LPTIM_CMP) ..... . 1437 31.7.7 LPTIM autoreload register (LPTIM_ARR) ..... 1438 31.7.8 LPTIM counter register (LPTIM_CNT) .
Page 34 Contents RM0440 33.7.4 AES data output register (AES_DOUTR) ..... 1490 33.7.5 AES key register 0 (AES_KEYR0) ......1490 33.7.6 AES key register 1 (AES_KEYR1) .
Page 35 RM0440 Contents 34.5 RTC interrupts ......... . . 1515 34.6 RTC registers .
Page 36 Contents RM0440 35.6.2 TAMP control register 2 (TAMP_CR2) ......1544 35.6.3 TAMP filter control register (TAMP_FLTCR) ....1545 35.6.4 TAMP interrupt enable register (TAMP_IER) .
Page 37 RM0440 Contents 36.6 USART interrupts ......... 1601 36.7 USART registers .
Page 38 Contents RM0440 37.4 LPUART interrupts ........1666 37.5 LPUART registers .
Page 39 RM0440 Contents 38.6 SPI interrupts ..........1719 38.7 I2S functional description .
Page 40 Contents RM0440 39.3.9 Internal FIFOs ......... . 1764 39.3.10 PDM Interface .
Page 41 RM0440 Contents 40.4.2 I2C pins and internal signals ....... 1819 40.4.3 I2C clock requirements .
Page 42 Contents RM0440 41.3 IWDG functional description ....... . . 1886 41.3.1 IWDG block diagram .
Page 43 RM0440 Contents 43.3.2 Operating modes ........1906 43.3.3 Message RAM .
Page 44 Contents RM0440 43.4.29 FDCAN Tx buffer add request register (FDCAN_TXBAR) ..1956 43.4.30 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 1957 43.4.31 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 1957 43.4.32 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) .
Page 45 RM0440 Contents 45.4.3 Physical layer protocol ........2003 45.4.4 UCPD BMC Transmitter .
Page 46 Using serial wire and releasing the unused debug pins as GPIOs . . 2046 46.5 STM32G4 Series JTAG TAP connection ..... . . 2046 46.6 ID codes and locking mechanism .
Page 47 STM32G4 Series ........
Page 48 STM32G4 Series memory density ........
Page 49 Table 49. STM32G4 Series peripherals interconnect matrix ......339 Table 50.
Page 50 List of tables RM0440 Table 100. Natural logarithm parameters ..........431 Table 101.
Page 51 RM0440 List of tables Table 152. ADC1/2 - External triggers for regular channels ....... . 587 Table 153.
Page 52 List of tables RM0440 Table 202. Update enable inputs and sources ......... . 807 Table 203.
Page 53 Table 260. STM32G4 Series general purpose timers ........
Page 54 Table 350. LPUART register map and reset values ........1691 Table 351. STM32G4 Series SPI and SPI/I2S implementation ......1694 Table 352.
Page 55 Table 401. STM32G4 Series USB implementation ........
Page 56 List of tables RM0440 Table 406. Reception status encoding ..........1992 Table 407.
Page 57 STM32G4 Series power supply overview ........
Page 58 List of figures RM0440 Figure 49. FMC block diagram............475 Figure 50.
Page 59 RM0440 List of figures Figure 101. Example of JSQR queue of context with empty queue (case JQM=1)....599 Figure 102. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion.
Page 60 List of figures RM0440 Figure 146. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first ..........638 Figure 147.
Page 61 RM0440 List of figures Figure 193. Push-pull mode example ..........829 Figure 194.
Page 62 List of figures RM0440 Figure 245. Auxiliary and main outputs during burst mode (DIDLx = 0) ..... . . 890 Figure 246.
Page 63 RM0440 List of figures Figure 295. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) ..1068 Figure 296. Output stage of capture/compare channel (channel 5, idem ch. 6) ....1069 Figure 297.
Page 64 List of figures RM0440 Figure 347. Down-counting encode error detection ........1119 Figure 348.
Page 65 RM0440 List of figures Figure 398. Retriggerable one pulse mode ..........1227 Figure 399.
Page 66 List of figures RM0440 Figure 448. Control circuit in external clock mode 1 ........1314 Figure 449.
Page 67 RM0440 List of figures Figure 497. AES block diagram ........... . . 1444 Figure 498.
Page 68 List of figures RM0440 Figure 546. Parity error detection using the 1.5 stop bits ....... . . 1588 Figure 547.
Page 69 RM0440 List of figures Figure 594. MSB justified 24-bit frame length ......... . 1724 Figure 595.
Page 70 List of figures RM0440 Figure 644. 10-bit address read access with HEAD10R=1 ....... . 1841 Figure 645.
Page 71: Documentation Conventions
RM0440 Documentation conventions Documentation conventions General information ®(a) ® The STM32G4 Series devices have an Arm Cortex -M4 with FPU core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit.
Page 72: Glossary
The present reference manual describes the superset of features for each product category. Refer to Table 2 for the list of features per category. Table 1. STM32G4 Series memory density Memory density Category 2 Category 3 STM32G471...
Page 73: Table 2. Product Specific Features
RM0440 Documentation conventions Table 2. Product specific features STM32G474/ STM32G473/ STM32G431/ Feature STM32G471 STM32G484 STM32G483 STM32G441 Flash 512K, Dual bank 512K, Dual bank 512K, Dual bank 128K, single bank 80K, parity check 80K, parity check 80K, parity check 16 K, parity check on the SRAM1 on the first 32K on the first 32K...
Page 74 Documentation conventions RM0440 Table 2. Product specific features (continued) STM32G474/ STM32G473/ STM32G431/ Feature STM32G471 STM32G484 STM32G483 STM32G441 Advanced control timers (TIM1/TIM8/ TIM1/8/20 TIM1/8/20 TIM1/8 TIM1/8 TIM20) General purpose timers (TIM2/TIM3/ TIM2/3/4/5 TIM2/3/4/5 TIM2/3/4/5 TIM2/3/4 TIM4/TIM5) General purpose timers TIM15/16/17 TIM15/16/17 TIM15/16/17 TIM15/16/17 (TIM15/TIM16/TIM17)
Page 75: System And Memory Overview
RM0440 System and memory overview System and memory overview System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Up to five masters: ® – Cortex -M4 with FPU core I-bus ® – Cortex -M4 with FPU core D-bus ®...
Page 76: I-Bus
System and memory overview RM0440 Figure 1. System architecture ® Cortex DMA1 DMA2 with FPU ICode FLASH 512 KB DCode SRAM1 CCM SRAM SRAM2 AHB1 peripherals AHB2 peripherals FSMC QUADSPI BusMatrix-S MSv45850V1 2.1.1 I-bus ® This bus connects the instruction bus of the Cortex -M4 with FPU core to the BusMatrix.
Page 77: S-Bus
RM0440 System and memory overview 2.1.3 S-bus ® This bus connects the system bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the internal SRAM, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the QUADSPI or the FMC.
Page 78: Memory Organization
RM0440 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 79: Memory Map And Register Boundary Addresses
RM0440 2.2.2 Memory map and register boundary addresses Figure 2. Memory map 0xFFFF FFFF 0xBFFF FFFF Reserved Cortex®-M4 0xA000 1800 with FPU QSPI registers Internal 0xA000 1000 Peripherals FMC registers 0xA000 0000 0xE000 0000 0x5FFF FFFF Reserved Reserved 0x5006 0C00 AHB2 0x4800 0000 0xC000 0000...
Page 80: Addresses
“Reserved”. For the detailed mapping of available memory and register areas, refer to the following table. The following table gives the boundary addresses of the peripherals available in the devices. Table 3. STM32G4 Series memory map and peripheral register boundary addresses Size Boundary address...
Page 81 RM0440 Table 3. STM32G4 Series memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 3400 - 0x47FF FFFF 127 MB Reserved 0x4002 3000 - 0x4002 33FF 1 KB Section 15.4.6: CRC register map...
Page 82 RM0440 Table 3. STM32G4 Series memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 AFFE - 0x4000 FFFF 23 KB Reserved 0x4000 AC00 - 0x4000 AFFF 1 KB FDCANs Section 43.4.38: FDCAN register map and...
Page 83: Bit Banding
In the STM32G4 Series devices both the peripheral registers and the SRAM are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The ®...
Page 84: Embedded Sram
0x20000300 (0x01: bit set; 0x00: bit reset). Embedded SRAM The STM32G4 Series category 3 devices feature up to 128 Kbytes SRAM: • 80 Kbytes SRAM1 (mapped at address 0x2000 0000) • 16 Kbytes SRAM2 (mapped at address 0x2001 4000) •...
Page 85: Parity Check
RM0440 2.4.1 Parity check On the Category 3 devices, a parity check is implemented on the first 32 Kbytes of SRAM1 and on the whole CCM SRAM. On the Category 2 devices, a parity check is implemented on the whole SRAM1 and CCM SRAM.
Page 86: Ccm Sram Read Protection
RM0440 Table 4. CCM SRAM organization (continued) Page number Start address End address Page 16 0x1000 4000 0x1000 43FF Page 17 0x1000 4400 0x1000 47FF Page 18 0x1000 4800 0x1000 4BFF Page 19 0x1000 4C00 0x1000 4FFF Page 20 0x1000 5000 0x1000 53FF Page 21 0x1000 5400...
Page 87: Flash Memory Overview
The information block. It is composed of three parts: – Option bytes for hardware and memory protection user configuration. – System memory that contains the ST proprietary code. – OTP (one-time programmable) area The Flash interface implements instruction access and data access based on the AHB protocol.
Page 88 RM0440 mode. Consequently, they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. Depending on the selected boot mode, main Flash memory, system memory or SRAM1 is accessible as follows: •...
Page 89: Table 6. Memory Mapping Versus Boot Mode/Physical Remap
3. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space. Embedded boot loader The embedded boot loader is located in the system memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode.
Page 90: Embedded Flash Memory (Flash) For Category 3 Devices
Embedded Flash memory (FLASH) for category 3 devices RM0440 Embedded Flash memory (FLASH) for category 3 devices Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.
Page 91: Flash Functional Description
USART, SPI, I2C, FDCAN, USB. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in Bank 1 only.
Page 92: Table 7. Flash Module - 512 Kb Dual Bank Organization (64 Bits Read Width)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Table 7. Flash module - 512 KB dual bank organization (64 bits read width) Size Flash area Flash memory addresses Name (bytes) 0x0800 0000 - 0x0800 07FF Page 0 0x0800 0800 - 0x0800 0FFF Page 1 0x0800 1000 - 0x0800 17FF Page 2...
Page 93: Error Code Correction (Ecc)
RM0440 Embedded Flash memory (FLASH) for category 3 devices Table 8. Flash module - 512 KB single bank organization (128 bits read width) Size Flash area Flash memory addresses Name (bytes) 0x0800 0000 - 0x0800 0FFF Page 0 0x0800 1000 - 0x0800 1FFF Page 1 0x0800 2000 - 0x0800 2FFF Page 2...
Page 94: Read Access Latency
Embedded Flash memory (FLASH) for category 3 devices RM0440 Single bank mode (DBANK=0, 128-bits data width) Data in Flash memory are 144-bits words: 8 bits are added per each double word. The ECC mechanism supports: • One error detection and correction •...
Page 95: Table 9. Number Of Wait States According To Cpu Clock (Hclk) Frequency
RM0440 Embedded Flash memory (FLASH) for category 3 devices Table 9. Number of wait states according to CPU clock (HCLK) frequency HCLK (MHz) Wait states (WS) (LATENCY) Range 1 Range 2 CORE CORE 0 WS (1 CPU cycles) ≤ 20 ≤...
Page 96: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Embedded Flash memory (FLASH) for category 3 devices RM0440 RCC_CFGR register and then (if needed) modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Page 97: Figure 3. Sequential 16-Bit Instructions Execution (64-Bit Read Data Width)
RM0440 Embedded Flash memory (FLASH) for category 3 devices Figure 3. Sequential 16-bit instructions execution (64-bit read data width) WAIT WITHOUT PREFETCH WAIT ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8 fetch fetch fetch fetch...
Page 98: Flash Program And Erase Operations
Data in option bytes block are not cacheable. 3.3.5 Flash program and erase operations The STM32G4 Series embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application into the microcontroller.
Page 99: Flash Main Memory Erase Sequences
RM0440 Embedded Flash memory (FLASH) for category 3 devices a write/erase operation is performed to the other bank (refer to Section 3.3.8: Read-while- write (RWW) available only in dual bank mode (DBANK=1)). The Flash erase and programming is only possible in the voltage scaling range 1. The VOS[1:0] bits in the PWR_CR1 must be programmed to 01b.
Page 100: Flash Main Memory Programming Sequences
Embedded Flash memory (FLASH) for category 3 devices RM0440 Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and the page erase request is aborted.
Page 101 RM0440 Embedded Flash memory (FLASH) for category 3 devices Standard programming The Flash memory programming sequence in standard mode is as follows: Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR).
Page 102 Embedded Flash memory (FLASH) for category 3 devices RM0440 bootloader. In dual bank mode (DBANK=1), perform a mass erase of the bank to program. If not, PGSERR is set. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR).
Page 103 RM0440 Embedded Flash memory (FLASH) for category 3 devices Programming errors Several kind of errors are detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero).
Page 104: Read-While-Write (Rww) Available Only In Dual Bank Mode
Embedded Flash memory (FLASH) for category 3 devices RM0440 In fast programming: all the data must be written successively. MISSERR is set if the previous data programmation is finished and the next data to program is not written yet. • FASTERR: Fast Programming Error In fast programming: FASTERR is set if one of the following conditions occurs: –...
Page 105 RM0440 Embedded Flash memory (FLASH) for category 3 devices Read from bank 1 while mass erasing bank 2 (or vice versa) While executing a program code from bank 1, it is possible to perform a mass erase operation on bank 2 (and vice versa). Follow the procedure below: Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR)
Page 106: Flash Option Bytes
Embedded Flash memory (FLASH) for category 3 devices RM0440 FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 4.4.2: Option bytes programming).
Page 107 [6:0] [6:0] [6:0] [6:0] SEC_ SEC_ 1FFFF828 Unused Unused _SIZE2 _SIZE2 User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA IRH_ PG10_ CCMSRAM SRAM WWDG IWGD_ IWDG_ IWDG_ Res. DBANK BFB2 Mode BOOT0...
Page 108 Embedded Flash memory (FLASH) for category 3 devices RM0440 Bit 25 CCMSRAM_RST: CCM SRAM erase when system reset 0: CCM SRAM erased when a system reset occurs 1: CCM SRAM is not erased when a system reset occurs Bit 24 SRAM_PE: SRAM1 and CCM SRAM parity check enable 0: SRAM1 and CCM SRAM parity check enable 1: SRAM1 and CCM SRAM parity check disable Bit 23 nBOOT1: Boot configuration...
Page 109 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active PCROP1 Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF Res. Res. Res. Res.
Page 110 PCROP1_END contains the last double-word of the bank 1 PCROP area. DBANK=0 PCROP1_END contains the last 2x double-word PCROP area for all memory. WRP1 Area A address option bytes Flash memory address: 0x1FFF 7818 ST production value: 0xFF00 FFFF Res. Res. Res. Res.
Page 111 RM0440 Embedded Flash memory (FLASH) for category 3 devices WRP2 Area A address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0xFF00 FFFF Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[6:0] Res. Res. Res. Res. Res.
Page 112 Embedded Flash memory (FLASH) for category 3 devices RM0440 PCROP2 Start address option bytes Flash memory address: 0x1FFFF808 ST production value: 0xFFFF FFFF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 113 RM0440 Embedded Flash memory (FLASH) for category 3 devices WRP1 Area B address option bytes Flash memory address: 0x1FFF F818 ST production value: 0xFF00 FFFF Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[6:0] Res. Res. Res. Res. Res.
Page 114: Option Bytes Programming
WRP2B_STRT contains the first page of the WRP second area for bank2. DBANK=0 WRP2B_STRT contains the first page of the WRP second area for all memory. Securable memory area Bank 2 option bytes Flash memory address: 0x1FFF F828 ST production value: 0xFF00 FF00 Res. Res. Res. Res.
Page 115 RM0440 Embedded Flash memory (FLASH) for category 3 devices Modifying user options The option bytes are programmed differently from a main memory user address. It is not possible to modify independently user options of bank 1 or bank 2. The users Options of the bank 1 are modified first.
Page 116 Embedded Flash memory (FLASH) for category 3 devices RM0440 FLASH_PCROP1/2ER, FLASH_WRP1/2AR, FLASH_WRP1/2BR). These registers are also used to modify options. If these registers are not modified by user, they reflects the options states of the system. See Section : Modifying user options for more details.
Page 117: Flash Memory Protection
RM0440 Embedded Flash memory (FLASH) for category 3 devices FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KByte).
Page 118 Embedded Flash memory (FLASH) for category 3 devices RM0440 Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.
Page 119: Table 13. Access Status Versus Protection Level And Execution Modes
RM0440 Embedded Flash memory (FLASH) for category 3 devices Only when both banks are erased, options are re-programmed with their previous values. This is also true for FLASH_PCROPxSR and FLASH_PCROPxER registers (x=1,2). Note: Full mass erase or partial mass erase is performed only when Level 1 is active and Level 0 requested.
Page 120: Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Table 13. Access status versus protection level and execution modes (continued) Debug/ BootFromRam/ User execution (BootFromFlash) Protection BootFromLoader Area level Read Write Erase Read Write Erase Backup registers CCM SRAM 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2.
Page 121: Table 14. Pcrop Protection
RM0440 Embedded Flash memory (FLASH) for category 3 devices For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address 0x0807 0004 (included): • if boot in flash is done in Bank 1, FLASH_PCROP1SR and FLASH_PCROP1ER registers must be programmed with: –...
Page 122: Write Protection (Wrp)
Embedded Flash memory (FLASH) for category 3 devices RM0440 1. When DBANK=1, the minimum PCROP area size is 2xdouble words: PCROPx_offset_strt and PCROPx_offset_end. When DBANK=0, the minimum PCROP area size is 2x(2xdouble words): PCROPx_offset_strt and PCROPx_offset_end. When DBANK=1, it is the user’s responsibility to make sure no overlapping occurs on the PCROP zones. 3.5.3 Write protection (WRP) The user area in Flash memory can be protected against unwanted write operations.
Page 123: Securable Memory Area
RM0440 Embedded Flash memory (FLASH) for category 3 devices If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also set for any write access to: –...
Page 124: Forcing Boot From Flash Memory
Embedded Flash memory (FLASH) for category 3 devices RM0440 In RDP level 2, the debugger is disabled by hardware, but in other RDP levels, the debugger can be disabled by software using the bit DBG_SWEN in the FLASH_ACR register. Figure 8 gives an example of managing DBG_SWEN and SEC_PROT bits.
Page 125: Flash Registers
RM0440 Embedded Flash memory (FLASH) for category 3 devices FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access DBG_ Res. Res. Res. Res. Res. Res. Res.
Page 126: Flash Power-Down Key Register (Flash_Pdkeyr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bit 11 ICRST: Instruction cache reset 0: Instruction cache is not reset 1: Instruction cache is reset This bit can be written only when the instruction cache is disabled. Bit 10 DCEN: Data cache enable 0: Data cache is disabled 1: Data cache is enabled Bit 9 ICEN: Instruction cache enable...
Page 127: Flash Key Register (Flash_Keyr)
RM0440 Embedded Flash memory (FLASH) for category 3 devices 3.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access KEYR[31:16] KEYR[15:0] Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing flash programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB...
Page 128: Flash Status Register (Flash_Sr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 3.7.5 Flash status register (FLASH_SR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 129 RM0440 Embedded Flash memory (FLASH) for category 3 devices Bit 7 PGSERR: Programming sequence error Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error.
Page 130: Flash Control Register (Flash_Cr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 3.7.6 Flash control register (FLASH_CR) Address offset: 0x14 Reset value: 0xC000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access SEC_ SEC_ OBL_ LOCK Res.
Page 131 RM0440 Embedded Flash memory (FLASH) for category 3 devices Bit 25 ERRIE: Error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SR is set to 1. 0: OPERR error interrupt disabled 1: OPERR error interrupt enabled Bit 24 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR is set to 1.
Page 132: Flash Ecc Register (Flash_Eccr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bits 9:3 PNB[6:0]: Page number selection These bits select the page to erase: 00000000: page 0 00000001: page 1 11111111: page 255 Bit 2 MER1: Bank 1 Mass erase This bit triggers the bank 1 mass erase (all bank 1 user pages) when set. Bit 1 PER: Page erase 0: page erase disabled 1: page erase enabled...
Page 133 RM0440 Embedded Flash memory (FLASH) for category 3 devices Bit 31 ECCD: ECC detection DBANK=1 Set by hardware when two ECC errors have been detected (only if ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this bit is set, a NMI is generated. Cleared by writing 1.
Page 134: Flash Option Register (Flash_Optr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bit 22 SYSF_ECC: System Flash ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash. Bit 21 BK_ECC: ECC fail bank DBANK=1 This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection.
Page 135 RM0440 Embedded Flash memory (FLASH) for category 3 devices Bit 31 Reserved, must be kept at reset value. Bit 30 IRHEN: Internal reset holder enable bit 0: Internal resets are propagated as simple pulse on NRST pin 1: Internal resets drives NRST pin low until it is seen as low level Bits 29:28 NRST_MODE[1:0] 00: Reserved 01: Reset Input only: a low level on the NRST pin generates system reset,...
Page 136: Flash Pcrop1 Start Address Register (Flash_Pcrop1Sr)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bit 16 IDWG_SW: Independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Reserved, must be kept cleared Bit 14 nRST_SHDW 0: Reset generated when entering the Shutdown mode 1: No reset generated when entering the Shutdown mode Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode...
Page 137: Flash Pcrop1 End Address Register (Flash_Pcrop1Er)
RM0440 Embedded Flash memory (FLASH) for category 3 devices Bits 31:15 Reserved, must be kept cleared Bits 14:0 PCROP1_STRT: PCROP area start offset DBANK=1 PCROP1_STRT contains the first double-word of the PCROP area for bank1. DBANK=0 PCROP1_STRT contains the first 2xdouble-word of the PCROP area for all memory.
Page 138: Flash Bank 1 Wrp Area A Address Register (Flash_Wrp1Ar)
Embedded Flash memory (FLASH) for category 3 devices RM0440 3.7.11 Flash Bank 1 WRP area A address register (FLASH_WRP1AR) Address offset: 0x2C Reset value: 0x00XX 00XX. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going, word, half-word and byte access Res.
Page 139: Flash Pcrop2 Start Address Register (Flash_Pcrop2Sr)
RM0440 Embedded Flash memory (FLASH) for category 3 devices Bits 31:23 Reserved, must be kept cleared Bits 22:16 WRP1B_END: WRP second area “B” end offset DBANK=1 WRP1B_END contains the last page of the WRP second area for bank1. DBANK=0 WRP1B_END contains the last page of the WPR second area for all memory. Bits 15:7 Reserved, must be kept cleared Bits 6:0 WRP1B_STRT: WRP second area “B”...
Page 140: Flash Bank 2 Wrp Area A Address Register (Flash_Wrp2Ar)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bits 31:15 Reserved, must be kept cleared Bits 14:0 PCROP2_END: PCROP area end offset DBANK=1 PCROP2_END contains the last double-word of the PCROP area for bank2. DBANK=0 PCROP2_END contains the last 2xdouble-word of the PCROP area for all the memory.
Page 141: Flash Bank 2 Wrp Area B Address Register (Flash_Wrp2Br)
RM0440 Embedded Flash memory (FLASH) for category 3 devices 3.7.16 Flash Bank 2 WRP area B address register (FLASH_WRP2BR) Address offset: 0x50 Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access Res.
Page 142: Flash Securable Area Bank2 Register (Flash_Sec2R)
Embedded Flash memory (FLASH) for category 3 devices RM0440 Bits 31:17 Reserved, must be kept cleared Bit 16 BOOT_LOCK: Unique boot entry point. When this bit is set, the boot is done from user flash only, whatever the RDP level. This bit can be reset by SW only in level0. In level 1, the only way to reset this bit is by doing a level regression (level 1 =>...
Page 143: Flash Register Map
RM0440 Embedded Flash memory (FLASH) for category 3 devices 3.7.19 FLASH register map Table 17. Flash interface - register map and reset values Offset Register LATENCY FLASH_ACR [3:0] 0x00 Reset value FLASH_ PDKEYR[31:0] PDKEYR 0x04 Reset value FLASH_KEYR KEYR[31:0] 0x08 Reset value FLASH_OPT OPTKEYR[31:0]...
Page 144 Embedded Flash memory (FLASH) for category 3 devices RM0440 Table 17. Flash interface - register map and reset values (continued) Offset Register FLASH_ WRP1B_END[6:0] WRP1B_STRT[6:0] WRP1BR 0x30 Reset value X X X X X X X X X X X X X X FLASH_ PCROP2_STRT[14:0] PCROP2SR...
Page 145: Embedded Flash Memory (Flash) For Category 2 Devices
RM0440 Embedded Flash memory (FLASH) for category 2 devices Embedded Flash memory (FLASH) for category 2 devices Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.
Page 146: Flash Functional Description
USART, SPI, I2C, USB. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP data cannot be erased and can be written only once.
Page 147: Error Code Correction (Ecc)
RM0440 Embedded Flash memory (FLASH) for category 2 devices 4.3.2 Error code correction (ECC) Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The ECC mechanism supports: • One error detection and correction •...
Page 148: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Embedded Flash memory (FLASH) for category 2 devices RM0440 When changing the CPU frequency, the following software sequences must be applied in order to tune the number of wait states needed to access the Flash memory: Increasing the CPU frequency: Program the new number of wait states to the LATENCY bits in the Flash access control register...
Page 149 RM0440 Embedded Flash memory (FLASH) for category 2 devices ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 170 MHz. Instruction prefetch ® The Cortex -M4 fetches the instruction over the ICode bus and the literal pool (constant/data) over the DCode bus.
Page 150: Figure 6. Sequential 16-Bit Instructions Execution (64-Bit Read Data Width)
Embedded Flash memory (FLASH) for category 2 devices RM0440 Figure 6. Sequential 16-bit instructions execution (64-bit read data width) WAIT WITHOUT PREFETCH WAIT ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8 fetch fetch fetch fetch...
Page 151: Flash Program And Erase Operations
Data in option bytes block are not cacheable. 4.3.5 Flash program and erase operations The STM32G4 Series embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application into the microcontroller.
Page 152: Flash Main Memory Erase Sequences
Embedded Flash memory (FLASH) for category 2 devices RM0440 During a program/erase operation to the Flash memory, any attempt to read the Flash memory stalls the bus. The read operation proceeds correctly once the program/erase operation has completed. Unlocking the Flash memory After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the...
Page 153: Flash Main Memory Programming Sequences
RM0440 Embedded Flash memory (FLASH) for category 2 devices Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set.
Page 154 Embedded Flash memory (FLASH) for category 2 devices RM0440 automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming.
Page 155 RM0440 Embedded Flash memory (FLASH) for category 2 devices Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero).
Page 156 Embedded Flash memory (FLASH) for category 2 devices RM0440 In fast programming: FASTERR is set if one of the following conditions occurs: – When FSTPG bit is set for more than 7ms which generates a time-out detection. – When the fast programming has been interrupted by a MISSERR, PGAERR, WRPERR or SIZERR.
Page 157: Flash Option Bytes
Unused END [6:0] _STRT [6:0] [6:0] [6:0] BOOT_ SEC_ BOOT_ SEC_ 1FFF7828 Unused Unused Unused Unused LOCK SIZE1 LOCK SIZE1 User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA RM0440 Rev 1 157/2083...
Page 158 Embedded Flash memory (FLASH) for category 2 devices RM0440 IRH_ PG10_ CCMSRAM SRAM WWDG IWGD_ IWDG_ IWDG_ Res. Res. Res. Res. Mode BOOT0 BOOT0 _RST BOOT1 STDBY STOP nRST_ nRST_ nRST_ Res. Res. BOR_LEV[2:0] RDP[7:0] SHDW STDBY STOP Bit 31 Reserved, must be kept at reset value. Bit 30 IRH_IN: Internal reset holder for PG10 0: IRH disabled 1: IRH enabled...
Page 159 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active PCROP1 Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF Res. Res. Res. Res.
Page 160 Bits 30:15 Reserved, must be kept at reset value. Bits 14:0 PCROP1_END: Bank 1 PCROP area end offset PCROP1_END contains the last double-word of the PCROP area. WRP1 Area A address option bytes Flash memory address: 0x1FFF 7818 ST production value: 0xFF00 FFFF Res. Res. Res. Res.
Page 161: Option Bytes Programming
RM0440 Embedded Flash memory (FLASH) for category 2 devices WRP2 Area A address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0xFF00 FFFF Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[6:0] Res. Res. Res. Res. Res.
Page 162 Embedded Flash memory (FLASH) for category 2 devices RM0440 Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory). Write OPTKEY1 = 0x08192A3B in the Flash option key register (FLASH_OPTKEYR). Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register. The user options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.
Page 163: Flash Memory Protection
RM0440 Embedded Flash memory (FLASH) for category 2 devices If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers: – For USR OPT option, the value of mismatch is all options at ‘1’, except for BOR_LEV which is “000”...
Page 164 Embedded Flash memory (FLASH) for category 2 devices RM0440 Level 0: no protection Read, program and erase operations into the Flash main memory area are possible. The option bytes, the CCM SRAM and the backup registers are also accessible by all operations.
Page 165: Table 23. Access Status Versus Protection Level And Execution Modes
RM0440 Embedded Flash memory (FLASH) for category 2 devices If the bit PCROP_RDP is cleared in the FLASH_PCROP1ER, the full mass erase is replaced by a partial mass erase that is successive page erases, except for the pages protected by PCROP. This is done in order to keep the PCROP code. Only when the Flash memory is erased, options are re-programmed with their previous values.
Page 166: Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory (FLASH) for category 2 devices RM0440 Table 23. Access status versus protection level and execution modes (continued) Debug/ BootFromRam/ User execution (BootFromFlash) Protection BootFromLoader Area level Read Write Erase Read Write Erase Option bytes Backup registers CCM SRAM 1.
Page 167: Write Protection (Wrp)
RM0440 Embedded Flash memory (FLASH) for category 2 devices Any read access performed through the D-bus to a PCROP protected area triggers RDERR flag error. Any PCROP protected address is also write protected and any write access to one of these addresses triggers WRPERR.
Page 168: Securable Memory Area
Embedded Flash memory (FLASH) for category 2 devices RM0440 For example, to protect by WRP from the address 0x0806 2800 (included) to the address 0x0807 07FF (included): • if boot in flash is selected, FLASH_WRP1AR register must be programmed with: –...
Page 169: Disabling Core Debug Access
RM0440 Embedded Flash memory (FLASH) for category 2 devices The size of the Securable memory area is defined by the SEC_SIZE1[7:0] bitfield of the FLASH_SEC register. It can be modified only in RDP Level 0. Its content is erased upon changing from RDP Level 1 to Level 0, even if it overlaps with PCROP pages.
Page 170: Flash Interrupts
Embedded Flash memory (FLASH) for category 2 devices RM0440 FLASH interrupts Table 26. Flash interrupt request Event flag/interrupt Interrupt enable control Interrupt event Event flag clearing method End of operation Write EOP=1 EOPIE Operation error OPERR Write OPERR=1 ERRIE Read error RDERR Write RDERR=1 RDERRIE...
Page 171: Flash Registers
RM0440 Embedded Flash memory (FLASH) for category 2 devices FLASH registers 4.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access DBG_ Res. Res. Res. Res. Res. Res. Res.
Page 172: Flash Power-Down Key Register (Flash_Pdkeyr)
Embedded Flash memory (FLASH) for category 2 devices RM0440 Bit 11 ICRST: Instruction cache reset 0: Instruction cache is not reset 1: Instruction cache is reset This bit can be written only when the instruction cache is disabled. Bit 10 DCEN: Data cache enable 0: Data cache is disabled 1: Data cache is enabled Bit 9 ICEN: Instruction cache enable...
Page 173: Flash Key Register (Flash_Keyr)
RM0440 Embedded Flash memory (FLASH) for category 2 devices 4.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access KEYR[31:16] KEYR[15:0] Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing flash programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB...
Page 174: Flash Status Register (Flash_Sr)
Embedded Flash memory (FLASH) for category 2 devices RM0440 4.7.5 Flash status register (FLASH_SR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 175: Flash Control Register (Flash_Cr)
RM0440 Embedded Flash memory (FLASH) for category 2 devices Bit 6 SIZERR: Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access).
Page 176 Embedded Flash memory (FLASH) for category 2 devices RM0440 Bit 31 LOCK: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Page 177: Flash Ecc Register (Flash_Eccr)
RM0440 Embedded Flash memory (FLASH) for category 2 devices Bit 16 START: Start This bit triggers an erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag.
Page 178: Flash Option Register (Flash_Optr)
Embedded Flash memory (FLASH) for category 2 devices RM0440 Bit 31 ECCD: ECC detection Set by hardware when two ECC errors have been detected (only if ECCC/ECCD are previously cleared). When this bit is set, a NMI is generated. Cleared by writing 1. Bit 30 ECCC: ECC correction Set by hardware when one ECC error has been detected and corrected (only if ECCC/ECCC2/ECCD/ECCD2 are previously cleared).
Page 179 RM0440 Embedded Flash memory (FLASH) for category 2 devices Bit 31 Reserved, must be kept at reset value. Bit 30 IRHEN: Internal reset holder enable bit 0: Internal resets are propagated as simple pulse on NRST pin 1: Internal resets drives NRST pin low until it is seen as low level Bits 29:28 NRST_MODE[1:0] 00: Reserved 01: Reset Input only: a low level on the NRST pin generates system reset,...
Page 180: Flash Pcrop1 Start Address Register (Flash_Pcrop1Sr)
Embedded Flash memory (FLASH) for category 2 devices RM0440 Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode 1: No reset generate when entering the Standby mode Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Reserved, must be kept cleared Bits10:8 BOR_LEV: BOR reset Level...
Page 181 RM0440 Embedded Flash memory (FLASH) for category 2 devices 4.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER) Address offset: 0x28 Reset value: 0xX000 XXXX. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going, word, half-word access. PCROP_RDP bit can be accessed with byte access.
Page 182 Embedded Flash memory (FLASH) for category 2 devices RM0440 Bits 22:16 WRP1A_END: WRP first area “A” end offset WRP1A_END contains the last page of WRP first area. Bits 15:7 Reserved, must be kept cleared Bits 6:0 WRP1A_STRT: WRP first area “A” start offset WRP1A_STRT contains the first page of WRP first area.
Page 183 RM0440 Embedded Flash memory (FLASH) for category 2 devices Bits 31:17 Reserved, must be kept cleared Bit 16 BOOT_LOCK: Unique boot entry point. When this bit is set, the boot is done from user flash only, whatever the RDP level. This bit can be reset by SW only in level0. In level 1, the only way to reset this bit is by doing a level regression (level 1 =>...
Page 184: Table 27. Flash Interface - Register Map And Reset Values
Embedded Flash memory (FLASH) for category 2 devices RM0440 4.7.14 FLASH register map Table 27. Flash interface - register map and reset values Offset Register LATENCY FLASH_ACR [3:0] 0x00 Reset value FLASH_ PDKEYR[31:0] PDKEYR 0x04 Reset value FLASH_KEYR KEYR[31:0] 0x08 Reset value FLASH_OPT OPTKEYR[31:0]...
Page 185 RM0440 Embedded Flash memory (FLASH) for category 2 devices Table 27. Flash interface - register map and reset values (continued) Offset Register FLASH_ WRP1B_END[6:0] WRP1B_STRT[6:0] WRP1BR 0x30 Reset value X X X X X X X X X X X X X X FLASH_ SEC_SIZE1[7:0] SEC1R...
Page 186 Power control (PWR) RM0440 Power control (PWR) Power supplies The STM32G4 Series devices require a 1.71 V to 3.6 V operating supply voltage (V Analog peripherals are supplied through independent power domain V • = 1.71 V to 3.6 V is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks.
Page 187: Figure 9. Stm32G4 Series Power Supply Overview
RM0440 Power control (PWR) Figure 9. STM32G4 Series power supply overview domain A/D converter D/A converters REF+ Comparators Operational amplifiers REF+ Voltage reference buffer USB transceivers domain I/O ring domain CORE Reset block Temp. sensor PLL, HSI16 Core SRAM1 SRAM2...
Page 188 Power control (PWR) RM0440 ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to a separate reference voltage lower than V is the highest voltage, REF+ REF+ represented by the full scale value, for an analog input (ADC) or output (DAC) signal. can be provided either by an external reference of by an internal buffered voltage REF+ reference (VREFBUF).
Page 189 RM0440 Power control (PWR) RTC functional description on page 1499) • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g.
Page 190: Table 28. Range 1 Boost Mode Configuration
Power control (PWR) RM0440 (MR) supplies full power to the V domain (core, memories and digital peripherals). CORE • In low-power run and low-power sleep modes, the main regulator is off and the low- power regulator (LPR) supplies low power to the V domain, preserving the CORE contents of the registers, SRAM1, SRAM2 and CCM SRAM.
Page 191 RM0440 Power control (PWR) The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 26 MHz.The Flash access time for a read access is increased as compared to Range 1; write and erase operations are not possible. Voltage scaling is selected through the VOS bit in the Section 5.4.1: Power control register 1 (PWR_CR1)
Page 192 Power control (PWR) RM0440 Set the R1MODE bit is in the PWR_CR5 register. Adjust the number of wait states according new frequency target in Range1 default mode. Configure and switch to new system frequency. Power supply supervisor 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry.
Page 193: Figure 10. Brown-Out Reset Waveform
RM0440 Power control (PWR) Figure 10. Brown-out reset waveform BORR4 BORF4 BORR3 BORF3 BORR2 BORF2 BORR1 BORF1 RSTTEMPO Reset with BOR off RSTTEMPO Reset with BOR on BORR4 BORF1 POR/BOR rising thresholds PDR/BOR falling thresholds MSv45389V4 1. The reset temporization t is present only for the BOR lowest threshold (V RSTTEMPO BOR0...
Page 194: Table 29. Pvm Features
Power control (PWR) RM0440 Figure 11. PVD thresholds V DD 100 mV threshold hysteresis PVD output MS31445V2 5.2.3 Peripheral Voltage Monitoring (PVM) Only V is monitored by default, as it is the only supply required for all system-related functions. The V can be independent from V and can be monitored with two peripheral voltage monitoring (PVM).
Page 195 RM0440 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.
Page 196: Figure 12. Low-Power Modes Possible Transitions
Power control (PWR) RM0440 In addition, the power consumption in Run mode can be reduced by one of the following means: • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. Figure 12.
Page 197: Table 30. Low-Power Mode Summary
RM0440 Power control (PWR) Table 30. Low-power mode summary Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock WFI or Return Sleep CPU clock OFF Same as before Any interrupt from ISR entering Sleep (Sleep-now or no effect on other clocks mode Sleep-on-exit)
Page 198: Table 31. Functionalities Depending On The Working Mode
Power control (PWR) RM0440 Table 31. Functionalities depending on the working mode Stop 0/1 Standby Shutdown Peripheral Sleep VBAT Flash memory SRAM1 SRAM2 CCM SRAM FSMC QUADSPI Backup Registers Brown-out reset (BOR) Programmable Voltage Detector (PVD) Peripheral Voltage Monitor (PVM) Oscillator HSI16 Oscillator HSI48 High Speed External (HSE)
Page 199 RM0440 Power control (PWR) Table 31. Functionalities depending on the working mode (continued) Stop 0/1 Standby Shutdown Peripheral Sleep VBAT SPIx (1,2,3,4) FDCANx (1,2,3) SAI1 ADCx (x=1,2,3,4,5) DACx (x=1,2,3,4) VREFBUF OPAMPx (x=1,2,3,4,5,6) COMPx (x=1,2,3,4,5,6,7) Temperature sensor Timers (TIMx) High resolution timer 1 (HRTIM1) Low-power timer 1 (LPTIM1) Independent watchdog (IWDG) Window watchdog (WWDG)
Page 200 Power control (PWR) RM0440 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.
Page 201: Table 32. Low-Power Run
RM0440 Power control (PWR) I/O states in Low-power run mode In Low-power run mode, all I/O pins keep the same state as in Run mode. Entering the Low-power run mode To enter the Low-power run mode, proceed as follows: Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in Flash access control register (FLASH_ACR).
Page 202 Power control (PWR) RM0440 – NVIC IRQ interrupt. ® - When SEVONPEND = 0 in the Cortex -M4 with FPU System Control register. By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
Page 203: Table 33. Sleep
RM0440 Power control (PWR) Table 33. Sleep Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending ® Refer to the Cortex -M4 with FPU System Control register.
Page 204: Table 34. Low-Power Sleep
-M4 with FPU System Control register. If WFI or Return from ISR was used for entry Interrupt: refer to Table 86: STM32G4 Series vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 2.3.2: Wakeup event management...
Page 205 RM0440 Power control (PWR) Refer to Table 35: Stop 0 mode for details on how to enter the Stop 0 mode. If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished.
Page 206: Table 35. Stop 0 Mode
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 86: STM32G4 Series vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode.
Page 207: Table 36. Stop 1 Mode
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 86: STM32G4 Series vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode.
Page 208 Power control (PWR) RM0440 I/O states in Standby mode In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G)), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G)), or can be kept in analog state. The RTC outputs on PC13 are functional in Standby mode.
Page 209: Table 37. Standby Mode
RM0440 Power control (PWR) Table 37. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 with FPU System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 210 Power control (PWR) RM0440 5.3.9 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V domain is consequently CORE powered off. The PLL, the HSI16, the LSI and the HSE oscillators are also switched off. SRAM1, SRAM2, CCM SRAM and register contents are lost except for registers in the Backup domain.
Page 211: Table 38. Shutdown Mode
RM0440 Power control (PWR) Table 38. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 with FPU System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 212 Power control (PWR) RM0440 PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode. Res.
Page 213 RM0440 Power control (PWR) 5.4.2 Power control register 2 (PWR_CR2) Address offset: 0x04 Reset value: 0x0000 0000. This register is reset when exiting Standby mode. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 214 Power control (PWR) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UCPD1 UCPD1_ EWUP EWUP EWUP EWUP EWUP EIWUL Res. Res. Res. Res. Res. Res. _DBDIS STDBY Bits 31:16 Reserved, must be kept at reset value. Bit 15 EIWUL: Enable internal wakeup line 0: Internal wakeup line disable.
Page 215 RM0440 Power control (PWR) Bit 2 EWUP3: Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.
Page 216 Power control (PWR) RM0440 Bit 2 WP3: Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 1 WP2: Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 0: Detection on high level (rising edge)
Page 217 RM0440 Power control (PWR) Bit 2 WUF3: Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register. Bit 1 WUF2: Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2.
Page 218 Power control (PWR) RM0440 Bit 9 REGLPF: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.
Page 219: Power Port A Pull-Up Control Register (Pwr_Pucra)
RM0440 Power control (PWR) Bit 2 CWUF3: Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. Bit 1 CWUF2: Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. Bit 0 CWUF1: Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
Page 220: Power Port B Pull-Up Control Register (Pwr_Pucrb)
Power control (PWR) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD14 Res. PD12 PD11 PD10 Bits 31:15 Reserved, must be kept at reset value. Bit 14 PD14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register.
Page 221: Power Port C Pull-Up Control Register (Pwr_Pucrc)
RM0440 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Res. Bits 31:16 Reserved, must be kept at reset value. Bits 15:5 PDy: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
Page 222: Power Port D Pull-Up Control Register (Pwr_Pucrd)
Power control (PWR) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
Page 223: Power Port E Pull-Up Control Register (Pwr_Pucre)
RM0440 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
Page 224: Power Port F Pull-Up Control Register (Pwr_Pucrf)
Power control (PWR) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
Page 225: Power Port G Pull-Up Control Register (Pwr_Pucrg)
RM0440 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.
Page 226: Power Control Register (Pwr_Cr5)
Power control (PWR) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.
Page 227: Pwr Register Map And Reset Value Table
RM0440 Power control (PWR) 5.4.23 PWR register map and reset value table Table 39. PWR register map and reset values Offset Register LPMS PWR_CR1 [1:0] [2:0] 0x00 Reset value PWR_CR2 PLS[2:0] 0x04 Reset value PWR_CR3 0x08 Reset value PWR_CR4 0x0C Reset value PWR_SR1 0x10...
Page 228 Power control (PWR) RM0440 Table 39. PWR register map and reset values (continued) Offset Register PWR_PDCRD 0x3C Reset value PWR_PUCRE 0x40 Reset value PWR_PDCRE 0x44 Reset value PWR_PUCRF 0x48 Reset value PWR_PDCRF 0x4C Reset value PWR_PUCRG 0x50 Reset value PWR_PDCRG 0x54 Reset value PWR_CR5...
Page 229: Reset And Clock Control (Rcc)
RM0440 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: Power-on reset (POR) or Brown-out reset (BOR).
Page 230: Figure 13. Simplified Diagram Of The Reset Circuit
Reset and clock control (RCC) RM0440 significant capacitive load. In case on an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption through the pull-up resistor. This mode is always active (independently of the option bytes setting) during each device power-on-reset (until option bytes are loaded): power on the device or wakeup from Shutdown mode.
Page 231: Rtc Domain Reset
RM0440 Reset and clock control (RCC) Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in User option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User option bytes.
Page 232 Reset and clock control (RCC) RM0440 All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB device FS, and RNG. This clock is derived (selected by software) from one of the four following sources: –...
Page 233 RM0440 Reset and clock control (RCC) LSI or LSE, or in external clock mode. • The RTC clock which is derived (selected by software) from one of the three following sources: – LSE clock – LSI clock – HSE clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE.
Page 234: Figure 14. Clock Tree
Reset and clock control (RCC) RM0440 Figure 14. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz OSC32_IN to PWR to AHB bus, core, memory and DMA / 1→16 HCLK FCLK Cortex free running clock PRESC SYSCLK / 1,2,..512...
Page 235: Hse Clock
RM0440 Reset and clock control (RCC) characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’. 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock...
Page 236: Hsi16 Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 237: Hsi48 Clock
RM0440 Reset and clock control (RCC) The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.9: Clock security system (CSS) on page 239. 6.2.3 HSI48 clock The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used directly for USB and for random number generator (RNG).
Page 238: Lsi Clock
Reset and clock control (RCC) RM0440 The LSE crystal is switched on and off using the LSEON bit in RTC domain control register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and low-power-...
Page 239: Clock Source Frequency Versus Voltage Scaling
RM0440 Reset and clock control (RCC) Clock source switching conditions: • Switching from HSE or HSI16 to PLL with AHB frequency (HCLK) higher than 80 MHz • Switching from PLL with HCLK higher than 80 MHz to HSE or HSI16 Transition state: •...
Page 240: Adc Clock
Reset and clock control (RCC) RM0440 LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL. The CSS on LSE is working in all modes except VBAT. It is working also under system reset (excluding power on reset).
Page 241: Timer Clock
RM0440 Reset and clock control (RCC) 6.2.13 Timer clock The timer clock frequencies are automatically defined by hardware. There are two cases: If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain. Otherwise, they are set to twice (×2) the frequency of the APB domain.
Page 242: Figure 16. Frequency Measurement With Tim15 In Capture Mode
Reset and clock control (RCC) RM0440 Figure 16. Frequency measurement with TIM15 in capture mode TIM 15 TI1SEL in TIM15_TISEL GPIO MS48963V1 The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the MCU.
Page 243: Figure 18. Frequency Measurement With Tim17 In Capture Mode
RM0440 Reset and clock control (RCC) Figure 18. Frequency measurement with TIM17 in capture mode TIM 17 TI1SEL in TIM17_TISEL GPIO RTC wakeup interrupt HSE/32 MSv45849V1 The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the MCU.
Page 244 Reset and clock control (RCC) RM0440 Calibration of the HSI16 For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSI16 system clocks (for this, the HSI16 should be used as the system clock source).
Page 245 RM0440 Reset and clock control (RCC) during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled. • Stop modes (Stop 0 and Stop 1) stops all the clocks in the V domain and disables CORE the PLL, the HSI16, and the HSE oscillators.
Page 246 Reset and clock control (RCC) RM0440 RCC registers 6.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 0063 HSEBYP is not affected by reset. Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res.
Page 247 RM0440 Reset and clock control (RCC) Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
Page 248 Reset and clock control (RCC) RM0440 Bit 31 Reserved, must be kept at reset value. Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16.
Page 249 RM0440 Reset and clock control (RCC) Bits 27:24 MCOSEL[3:0]: Microcontroller clock output Set and cleared by software. 0000: MCO output disabled, no clock on MCO 0001: SYSCLK system clock selected 0010: Reserved, must be kept at reset value 0011: HSI16 clock selected 0100: HSE clock selected 0101: Main PLL clock selected 0110: LSI clock selected...
Page 250 Reset and clock control (RCC) RM0440 Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: Reserved, must be kept at reset value 01: HSI16 oscillator used as system clock 10: HSE used as system clock 11: PLL used as system clock Bits 1:0 SW[1:0]: System clock switch...
Page 251 RM0440 Reset and clock control (RCC) Bits 26:25 PLLR[1:0]: Main PLL division factor for PLL “R” clock (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled.
Page 252 Reset and clock control (RCC) RM0440 Bit 16 PLLPEN: Main PLL PLL “P” clock output enable Set and reset by software to enable the PLL “P” clock output of the PLL. In order to save power, when the PLL “P” clock output of the PLL is not used, the value of PLLPEN should be 0.
Page 253 RM0440 Reset and clock control (RCC) 6.4.5 Clock interrupt enable register (RCC_CIER) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 254 Reset and clock control (RCC) RM0440 Bit 2 Reserved, must be kept at reset value. Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 0 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator...
Page 255 RM0440 Reset and clock control (RCC) Bit 5 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit 4 HSERDYF: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Page 256 Reset and clock control (RCC) RM0440 Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. 0: No effect 1: Clear the HSI48RDYC flag Bit 9 LSECSSC: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag.
Page 257 RM0440 Reset and clock control (RCC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH FMAC CORDIC DMAMUX1 DMA2 DMA1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:13 Reserved, must be kept at reset value. Bit 12 CRCRST: CRC reset Set and cleared by software.
Page 258 Reset and clock control (RCC) RM0440 6.4.9 AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access DAC4 DAC3 DAC2 DAC1 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 259 RM0440 Reset and clock control (RCC) Bit 14 ADC345RST: ADC345 reset Set and cleared by software. 0: No effect 1: Reset ADC345 Bit 13 ADC12RST: ADC12 reset Set and cleared by software. 0: No effect 1: Reset ADC12 interface Bits 12:7 Reserved, must be kept at reset value. Bit 6 GPIOGRST: IO port G reset Set and cleared by software.
Page 260 Reset and clock control (RCC) RM0440 6.4.10 AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x30 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 261 RM0440 Reset and clock control (RCC) Bit 31 LPTIM1RST: Low Power Timer 1 reset Set and cleared by software. 0: No effect 1: Reset LPTIM1 Bit 30 I2C3RST: I2C3 reset Set and cleared by software. 0: No effect 1: Reset I2C3 interface Bit 29 Reserved, must be kept at reset value.
Page 262 Reset and clock control (RCC) RM0440 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset...
Page 263 RM0440 Reset and clock control (RCC) 6.4.12 APB1 peripheral reset register 2 (RCC_APB1RSTR2) Address offset: 0x3C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 264 Reset and clock control (RCC) RM0440 Bits 31:27 Reserved, must be kept at reset value. Bit 26 HRTIM1RST: HRTIM1 reset Set and cleared by software. 0: No effect 1: Reset HRTIM1 Bits 25:22 Reserved, must be kept at reset value. Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset Set and cleared by software.
Page 265 RM0440 Reset and clock control (RCC) Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bits 10:1 Reserved, must be kept at reset value. Bit 0 SYSCFGRST: SYSCFG + COMP + OPAMP + VREFBUF reset 0: No effect 1: Reset SYSCFG + COMP + OPAMP + VREFBUF 6.4.14...
Page 266 Reset and clock control (RCC) RM0440 Bit 2 DMAMUX1EN: DMAMUX1 clock enable Set and reset by software. 0: DMAMUX1 clock disabled 1: DMAMUX1 clock enabled Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disable 1: DMA2 clock enable Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software.
Page 267 RM0440 Reset and clock control (RCC) Bit 18 DAC3EN: DAC3 clock enable Set and cleared by software. 0: DAC3 clock disabled 1: DAC3 clock enabled Bit 17 DAC2EN: DAC2 clock enable Set and cleared by software. 0: DAC2 clock disabled 1: DAC2 clock enabled Bit 16 DAC1EN: DAC1 clock enable Set and cleared by software.
Page 268 Reset and clock control (RCC) RM0440 Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 0 GPIOAEN: IO port A clock enable...
Page 269 RM0440 Reset and clock control (RCC) 6.4.17 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) Address: 0x58 Reset value: 0x0000 0400 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 270 Reset and clock control (RCC) RM0440 Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 UART5EN: UART5 clock enable Set and cleared by software. 0: UART5 clock disabled 1: UART5 clock enabled Bit 19 UART4EN: UART4 clock enable Set and cleared by software.
Page 271 RM0440 Reset and clock control (RCC) Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software.
Page 272 Reset and clock control (RCC) RM0440 Bits 31:9 Reserved, must be kept at reset value. Bit 8 UCPD1EN: UCPD1 clock enable Set and cleared by software. 0: UCPD1 clock disable 1: UCPD1 clock enable Bits 7:2 Reserved, must be kept at reset value. Bit 1 I2C4EN: I2C4 clock enable Set and cleared by software 0: I2C4 clock disabled...
Page 273 RM0440 Reset and clock control (RCC) 6.4.19 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 274 Reset and clock control (RCC) RM0440 Bit 15 SPI4EN: SPI4 timer clock enable Set and cleared by software. 0: SPI4 timer clock disabled 1: SPI4 timer clock enabled Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 TIM8EN: TIM8 timer clock enable Set and cleared by software.
Page 275 RM0440 Reset and clock control (RCC) Bits 31:13 Reserved, must be kept at reset value. Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes Set and cleared by software. 0: CRC clocks disabled by the clock gating during Sleep and Stop modes 1: CRC clocks enabled by the clock gating during Sleep and Stop modes Bits 11:10 Reserved, must be kept at reset value.
Page 276 Reset and clock control (RCC) RM0440 6.4.21 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) Address offset: 0x6C Reset value: 0x050F 667F Access: no wait state, word, half-word and byte access AESM DAC4 DAC3 DAC2 DAC1 Res. Res.
Page 277 RM0440 Reset and clock control (RCC) Bit 14 ADC345SMEN: ADC345 clock enable Set and cleared by software. 0: ADC345 clock disabled 1: ADC345 clock enabled Bit 13 ADC12SMEN: ADC12 clocks enable during Sleep and Stop modes Set and cleared by software. 0: ADC12 clocks disabled by the clock gating during Sleep and Stop modes 1: ADC12 clocks enabled by the clock gating...
Page 278 Reset and clock control (RCC) RM0440 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 6.4.22 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR)
Page 279 RM0440 Reset and clock control (RCC) Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 1: LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes Bit 30 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes Set and cleared by software.
Page 280 Reset and clock control (RCC) RM0440 Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART2 clocks disabled by the clock gating during Sleep and Stop modes 1: USART2 clocks enabled by the clock gating during Sleep and Stop modes Bit 16 Reserved, must be kept at reset value.
Page 281 RM0440 Reset and clock control (RCC) Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM3 clocks disabled by the clock gating during Sleep and Stop modes 1: TIM3 clocks enabled by the clock gating during Sleep and Stop modes Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software.
Page 282 Reset and clock control (RCC) RM0440 6.4.25 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0437 F801 Access: word, half-word and byte access HRTIM1 SAI1 TIM20 TIM17 TIM16 TIM15 Res. Res. Res. Res. Res.
Page 283 RM0440 Reset and clock control (RCC) Bit 15 SPI4SMEN: SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI4 clocks disabled by the clock gating during Sleep and Stop modes 1: SPI4 clocks enabled by the clock gating during Sleep and Stop mode Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes Set and cleared by software.
Page 284 Reset and clock control (RCC) RM0440 Bits 31:30 ADC345SEL[1:0]: ADC3/4/5 clock source selection These bits are set and cleared by software to select the clock source used by the ADC345 interface. 00: No clock selected 01: PLL “P” clock selected as ADC345 clock 10: System clock selected as ADC3/4/5 clock 11: Reserved.
Page 285 RM0440 Reset and clock control (RCC) Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 00: PCLK selected as I2C3 clock 01: System clock (SYSCLK) selected as I2C3 clock 10: HSI16 clock selected as I2C3 clock 11: Reserved Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection...
Page 286 Reset and clock control (RCC) RM0440 Bits 5:4 USART3SEL[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock 01: System clock (SYSCLK) selected as USART3 clock 10: HSI16 clock selected as USART3 clock 11: LSE clock selected as USART3 clock Bits 3:2 USART2SEL[1:0]: USART2 clock source selection...
Page 287 RM0440 Reset and clock control (RCC) Bits 31:26 Reserved, must be kept at reset value. Bit 25 LSCOSEL: Low speed clock output selection Set and cleared by software. 0: LSI clock selected 1: LSE clock selected Bit 24 LSCOEN: Low speed clock output enable Set and cleared by software.
Page 288 Reset and clock control (RCC) RM0440 Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’ medium low driving capability 10: ‘Xtal mode’ medium high driving capability 11: ‘Xtal mode’...
Page 289 RM0440 Reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs.
Page 290 Reset and clock control (RCC) RM0440 Bits 22:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.
Page 291: Table 41. Rcc Register Map And Reset Values
RM0440 Reset and clock control (RCC) 6.4.30 Peripherals independent clock configuration register (RCC_CCIPR2) Address: 0x9C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. QSPISEL Res.
Page 292 Reset and clock control (RCC) RM0440 Table 41. RCC register map and reset values (continued) Offset Register PLLR PLLQ PLLN PLLM RCC_PLL PLLPDIV[4:0] [1:0] [1:0] [6:0] [3:0] CFGR 0x0C [1:0] 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset value RCC_CIER 0x18...
Page 293 RM0440 Reset and clock control (RCC) Table 41. RCC register map and reset values (continued) Offset Register RCC_ APB2RSTR 0x40 0 0 0 0 0 0 0 0 Reset value RCC_AHB1 0x48 0 0 0 0 0 Reset value RCC_AHB2 0x4C 0 0 0 0 0 0 0 0 0 0 0...
Page 294 Reset and clock control (RCC) RM0440 Table 41. RCC register map and reset values (continued) Offset Register RCC_ AHB2SMENR 0x6C 1 1 1 1 1 1 1 1 1 1 1 Reset value RCC_ AHB3SMENR 0x70 Reset value RCC_ APB1SM 0x78 ENR1 1 1 1 1 1 1 1...
Page 295 RM0440 Reset and clock control (RCC) Table 41. RCC register map and reset values (continued) Offset Register HSI48CAL[8:0] RCC_CRRCR 0x98 X X X X X X X X X Reset value RCC_CCIPR2 0x9C Reset value Refer to Section 2.2 on page 78 for the register boundary addresses.
Page 296 Clock recovery system (CRS) RM0440 Clock recovery system (CRS) Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal.
Page 297: Figure 20. Crs Block Diagram
RM0440 Clock recovery system (CRS) CRS functional description 7.3.1 CRS block diagram Figure 20. CRS block diagram CRS_SYNC GPIO SYNCSRC SWSYNC OSC32_IN SYNC divider (/1, /2, /4,…, /128) OSC32_OUT SYNC USB_DP FELIM USB_DM TRIM FEDIR FECAP 16-bit counter RC 48 MHz RELOAD HSI48 To SYSCLK,...
Page 298: Figure 21. Crs Counter Behavior
Clock recovery system (CRS) RM0440 7.3.3 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated.
Page 299 RM0440 Clock recovery system (CRS) 7.3.4 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register –...
Page 300: Table 42. Effect Of Low-Power Modes On Crs
Clock recovery system (CRS) RM0440 FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (f ) * STEP[%] / 100% / 2...
Page 301 RM0440 Clock recovery system (CRS) CRS registers Refer to Section 1.2 on page 71 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 7.6.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 4000 Res.
Page 302 Clock recovery system (CRS) RM0440 Bit 3 ESYNCIE: Expected SYNC interrupt enable 0: Expected SYNC (ESYNCF) interrupt disabled 1: Expected SYNC (ESYNCF) interrupt enabled Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled...
Page 303 RM0440 Clock recovery system (CRS) Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32...
Page 304 Clock recovery system (CRS) RM0440 Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken.
Page 305 RM0440 Clock recovery system (CRS) 7.6.4 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNC SYNC Res. Res. Res. Res.
Page 306: Table 44. Crs Register Map And Reset Values
Clock recovery system (CRS) RM0440 7.6.5 CRS register map Table 44. CRS register map and reset values Offset Register TRIM[6:0] CRS_CR 0x00 Reset value SYNC SYNC CRS_CFGR FELIM[7:0] RELOAD[15:0] 0x04 [1:0] [2:0] Reset value CRS_ISR FECAP[15:0] 0x08 Reset value CRS_ICR 0x0C Reset value Refer to...
Page 307 RM0440 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 308: Figure 22. Basic Structure Of An I/O Port Bit
General-purpose I/Os (GPIO) RM0440 Figure 22 Figure 23 show the basic structures of a standard and a 5-Volt tolerant I/O port bit, respectively. Table 45 gives the possible port bit configurations. Figure 22. Basic structure of an I/O port bit Analog To on-chip peripheral...
Page 309: Table 45. Port Bit Configuration Table
RM0440 General-purpose I/Os (GPIO) Table 45. Port bit configuration table MODE(i) OSPEED(i) PUPD(i) OTYPE(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 310 General-purpose I/Os (GPIO) RM0440 8.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up •...
Page 311 RM0440 General-purpose I/Os (GPIO) – Configure the desired I/O as an alternate function in the GPIOx_MODER register. • Additional functions: – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers.
Page 312 General-purpose I/Os (GPIO) RM0440 8.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same).
Page 313: Figure 24. Input Floating/Pull Up/Pull Down Configurations
RM0440 General-purpose I/Os (GPIO) Figure 24 shows the input configuration of the I/O port bit. Figure 24. Input floating/pull up/pull down configurations Read V DDIOx V DDIOx on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull...
Page 314: Figure 25. Output Configuration
General-purpose I/Os (GPIO) RM0440 Figure 25. Output configuration Read DDIOx TTL Schmitt DDIOx trigger on/off protection Write Input driver diode pull I/O pin Output driver DDIOx on/off P-MOS protection pull down diode Output control Read/write N-MOS Push-pull or Open-drain MS31478V1 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function:...
Page 315: Figure 27. High Impedance-Analog Configuration
RM0440 General-purpose I/Os (GPIO) 8.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 316 General-purpose I/Os (GPIO) RM0440 8.3.15 Using PB8 as GPIO PB8 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in the user option byte, it switches from the input mode to the analog input mode: •...
Page 317 RM0440 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A to G) Address offset:0x00...
Page 318 General-purpose I/Os (GPIO) RM0440 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to G) Address offset: 0x08 Reset value: 0x0C00 0000 (for port A) Reset value: 0x0000 0000 (for the other ports) OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8 [1:0]...
Page 319 RM0440 General-purpose I/Os (GPIO) 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to G) Address offset: 0x10 Reset value: 0x0000 XXXX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID15 ID14 ID13 ID12...
Page 320 General-purpose I/Os (GPIO) RM0440 Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority.
Page 321 RM0440 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 322 General-purpose I/Os (GPIO) RM0440 Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6...
Page 323 RM0440 General-purpose I/Os (GPIO) Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6...
Page 324: Table 46. Gpio Register Map And Reset Values
General-purpose I/Os (GPIO) RM0440 8.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 46. GPIO register map and reset values Offset Register name GPIOA_MODER 0x00 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 GPIOB_MODER 0x00 Reset value...
Page 325 RM0440 General-purpose I/Os (GPIO) Table 46. GPIO register map and reset values (continued) Offset Register name GPIOx_ODR (where x = ) 0x14 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BSRR (where x = ) 0x18 Reset value 0 0 0 0...
Page 326 System configuration controller (SYSCFG) RM0440 System configuration controller (SYSCFG) SYSCFG main features The STM32G4 Series devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
Page 327 RM0440 System configuration controller (SYSCFG) Bits 2:0 MEM_MODE: Memory mapping selection These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pin and the option bit setting.
Page 328 System configuration controller (SYSCFG) RM0440 Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
Page 329: Table 47. Boosten And Anaswvdd Set/Reset
RM0440 System configuration controller (SYSCFG) Table 47. BOOSTEN and ANASWVDD set/reset VDDA BOOSTEN ANASWVDD > 2.4 V > 2.4 V < 2.4 V < 2.4 V < 2.4 V 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 EXTI3[3:0] EXTI2[3:0]...
Page 330 System configuration controller (SYSCFG) RM0440 Bits 7:4 EXTI1[3:0]: EXTI 1 configuration bits These bits are written by software to select the source input for the EXTI1 external interrupt. 0000: PA[1] pin 0001: PB[1] pin 0010: PC[1] pin 0011: PD[1] pin 0100: PE[1] pin 0101: PF[1] pin 0110: PG[1] pin...
Page 331 RM0440 System configuration controller (SYSCFG) Bits 11:8 EXTI6[3:0]: EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt. 0000: PA[6] pin 0001: PB[6] pin 0010: PC[6] pin 0011: PD[6] pin 0100: PE[6] pin 0101: PF[6] pin 0110: PG[6] pin...
Page 332 System configuration controller (SYSCFG) RM0440 Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 0000: PA[11] pin 0001: PB[11] pin 0010: PC[11] pin 0011: PD[11] pin 0100: PE[11] pin 0101: PF[11] pin Bits 11:8 EXTI10[3:0]: EXTI 10 configuration bits...
Page 333 RM0440 System configuration controller (SYSCFG) 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI15[3:0]: EXTI 15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt.
Page 334 System configuration controller (SYSCFG) RM0440 Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.2.7 SYSCFG CCM SRAM control and status register (SYSCFG_SCSR) Address offset: 0x18 System reset value: 0x0000 0000 Bits 31:2 Reserved, must be kept at reset value Bit 1 CCMBSY: CCM SRAM busy by erase operation 0: No CCM SRAM erase operation is on going.
Page 335 RM0440 System configuration controller (SYSCFG) 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x1C System reset value: 0x0000 0000 ECCL PVDL rc_w1 Bits 31:9 Reserved, must be kept at reset value Bit 8 SPF: SRAM1 and CCM SRAM parity error flag This bit is set by hardware when an SRAM1 or CCM SRAM parity error is detected.
Page 336 System configuration controller (SYSCFG) RM0440 ® Bit 0 CLL: Cortex -M4 LOCKUP (Hardfault) output enable bit This bit is set by software and cleared only by a system reset. It can be used to ® enable and lock the connection of Cortex -M4 with FPU LOCKUP (Hardfault) output to TIM1/8/15/16/17/20 break input and hrtim_sys_flt input of HRTIM1.
Page 337: Table 48. Syscfg Register Map And Reset Values
RM0440 System configuration controller (SYSCFG) 9.2.11 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 48. SYSCFG register map and reset values Offset Register SYSCFG_ MEM_ MODE MEMRMP 0x00 Reset value SYSCFG_CFGR1 FPU_IE[5..0] 0x04 Reset value EXTI3...
Page 338 Peripherals interconnect matrix RM0440 Peripherals interconnect matrix 10.1 Introduction Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections remove software latency and allow design of predictable system.
Page 339: Table 49. Stm32G4 Series Peripherals Interconnect Matrix
RM0440 Peripherals interconnect matrix 10.2 Connection summary (1) (2) Table 49. STM32G4 Series peripherals interconnect matrix Destination Source TIM1 1 1 1 1 19 19 19 19 19 15 15 15 15 15 15 15 TIM2 10 19 19 19 19 19...
Page 340 Peripherals interconnect matrix RM0440 (1) (2) Table 49. STM32G4 Series peripherals interconnect matrix (continued) Destination Source OPAMP6 - DAC1 DAC2 DAC3 DAC4 4 4 4 HSI16 EXT1 2 2 2 2 2 2 2 2 2 COMP1 COMP2 COMP3 COMP4...
Page 341: Table 50. Interconnect 1
RM0440 Peripherals interconnect matrix (1) (2) Table 49. STM32G4 Series peripherals interconnect matrix (continued) Destination Source COMP6 COMP7 SYST ERR 18 18 18 18 18 1. Numbers inside table link to corresponding interconnect number detailed in Section 10.3: Interconnection details.
Page 342: Table 51. Interconnect 12
Peripherals interconnect matrix RM0440 The burst mode controller counter can be clocked by general purpose timers as well as shown in the Table Table 51. Interconnect 12 HRTIM Burst mode trigger event/ clock signal HRTIM Burst mode trigger event/ clock signal assignment hrtim_bm_trg tim7_trgo...
Page 343 RM0440 Peripherals interconnect matrix Triggering signals The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8/TIM20) following a configurable timer event. The input (to slave) is on signals TIMx_ITRx The input and output signals for TIM1/TIM8/TIM20 are shown in Figure 266: Advanced- control timer block diagram.
Page 344 Peripherals interconnect matrix RM0440 Table 54. Interconnect 19 (continued) ADC triggers signals assignment ADC trigger selection EXTSEL[4:0] or ADC1/2 ADC3/4/5 JEXTSEL[4:0] Regular Injected Regular Injected tim20_cc3 hrtim_adc_trg4 hrtim_adc_trg4 hrtim_adc_trg4 hrtim_adc_trg1 hrtim_adc_trg5 hrtim_adc_trg1 hrtim_adc_trg5 hrtim_adc_trg3 hrtim_adc_trg6 hrtim_adc_trg3 hrtim_adc_trg6 hrtim_adc_trg5 hrtim_adc_trg7 hrtim_adc_trg5 hrtim_adc_trg7 hrtim_adc_trg6 hrtim_adc_trg8...
Page 345 RM0440 Peripherals interconnect matrix 10.3.3 From ADC (ADCx) to timer (TIMx, HRTIM) See please Table 62: Interconnect 2 Table 70.: Interconnect 10 ADCs Analog watchdogs are connected to TIM1/8/20 for digital power applications (cycle- bycycle current regulation with ADC). A description of the ADC analog watchdog setting is provided in: Section 20.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx,...
Page 346 Peripherals interconnect matrix RM0440 Table 55. Interconnect 20 (continued) DAC triggers signals assignment DAC trigger selection DAC1 DAC2 DAC3 DAC4 (TSELx[3:0], STRSTTRIG Update/ Update/ Update Update/ SELx[3:0]) reset reset /reset reset hrtim_dac hrtim_dac hrtim_dac_ hrtim_step hrtim_dac_ hrtim_step hrtim_step hrtim_step _reset_trg _reset_trg reset_trg4 _trig4...
Page 347: Table 56. Interconnect 17
RM0440 Peripherals interconnect matrix 10.3.6 From RTC, COMPx to low-power timer (LPTIM1) Table 56. Interconnect 17 LPTIM trigger input signal (TRIGSEL[3:0]) LPTIM1 trigger source assignment lptim1_ext_trig0 LPTIM1_ETR lptim1_ext_trig1 rtc_alra_trg lptim1_ext_trig2 rtc_alrb_trg lptim1_ext_trig3 RTC_TAMP1 lptim1_ext_trig4 RTC_TAMP2 lptim1_ext_trig5 RTC_TAMP3 lptim1_ext_trig6 comp1_out lptim1_ext_trig7 comp2_out lptim1_ext_trig8 comp3_out...
Page 348: Table 57. Interconnect 15
Peripherals interconnect matrix RM0440 10.3.7 From timer (TIMx) to comparators (COMPx) Table 57. Interconnect 15 Comparator blanking source assignment Comparator blanking signal BLANKSEL[2:0] COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 tim1_oc5 tim1_oc5 tim1_oc5 tim3_oc4 tim2_oc3 tim8_oc5 tim1_oc5 tim2_oc3 tim2_oc3 tim3_oc3 tim8_oc5 tim8_oc5 tim2_oc4...
Page 349 RM0440 Peripherals interconnect matrix Table 58. Interconnect 21 (continued) ADC channel source assignment ADC channel number ADC1 ADC2 ADC3 ADC4 ADC5 opamp4_int PB14 PB13 PB15 _vout PD10 PD10 PD10 PD11 PD11 PD11 PD12 PD12 PD12 IN10 PD13 PD13 PD13 PB12/OPAMP4 IN11 PD14 PD14...
Page 350: Table 60. Interconnect 23
Peripherals interconnect matrix RM0440 Table 59. Interconnect 22 (continued) Source Destination DAC1 DAC2 DAC3 DAC4 COMP5 COMP6 COMP7 OPAMP1 OPAMP2 OPAMP3 OPAMP4 OPAMP5 OPAMP6 Table 60. Interconnect 23 Comparator Comparators input/output signals assignment input/output signals GPIO DAC output VREFINT scaler DAC1_ DAC3_ VREF...
Page 351 RM0440 Peripherals interconnect matrix Table 60. Interconnect 23 (continued) Comparator Comparators input/output signals assignment input/output GPIO DAC output VREFINT scaler signals PD12 PB13 DAC1_ DAC4_ VREF COMP5 PD13 PB10 VREF VREF VREF PD11 PB11 DAC2_ DAC4_ VREF COMP6 PD10 PB15 VREF VREF VREF...
Page 352 Peripherals interconnect matrix RM0440 Table 61. Interconnect 24 (continued) Operational amplifier input/output signals assignment Operational amplifier ADC input on ADC internal input/output signals GPIO DAC output GPIO input VINP PB14 PD12 DAC4_CH2 OPAMP5 VINM PB15 VOUT ADC5_IN1 ADC5_IN3 VINP PB12 PB13 DAC3_CH1 OPAMP6...
Page 353: Table 63. Interconnect 3
RM0440 Peripherals interconnect matrix Table 62. Interconnect 2 (continued) Timer external Timer external trigger signals assignment trigger input TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM20 signal adc12_ tim3_ tim2_ adc12_ adc345_ timx_etr8 tim3_etr tim2_etr awd1_m awd1_s1 awd2_m adc12_ tim5_ tim3_ adc12_ adc345_ timx_etr9...
Page 354 Peripherals interconnect matrix RM0440 Table 64. Interconnect 4 Timer Timer TI1 signals assignment input TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM15 TIM16 TIM17 TIM20 signal TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM15 TIM16 TIM17 TIM20 timx_ external external external external external external external...
Page 355: Table 65. Interconnect 5
RM0440 Peripherals interconnect matrix Table 65. Interconnect 5 Timer Timer TI2 signals assignment TI2 input TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM15 TIM20 signal TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM15 TIM20 timx_ external external external external external external external external ti2_in0 TI2 input...
Page 356: Table 68. Interconnect 8
Peripherals interconnect matrix RM0440 The timer break input features two channels: • A break channel which gathers both application fault (from input pins and built-in comparators) and system-level fault (clock failure, parity error, ...). • A break2 channel which only includes application faults (from input pins and built-in comparators).
Page 357: Table 70. Interconnect 10
RM0440 Peripherals interconnect matrix Table 70. Interconnect 10 HRTIM external event signal assignment HRTIM external EExSRC[1:0]=0 event input signal EExSRC[1:0]=1 EExSRC[1:0]=2 EExSRC[1:0]=3 (from GPIO pin) hrtim_eev1[4:1] HRTIM_EEV1 comp2_out tim1_trgo adc1_AWD1 hrtim_eev2[4:1] HRTIM_EEV2 comp4_out tim2_trgo adc1_AWD2 hrtim_eev3[4:1] HRTIM_EEV3 comp6_out tim3_trgo adc1_AWD3 hrtim_eev4[4:1] HRTIM_EEV4 comp1_out...
Page 358: Table 72. Interconnect 18
Peripherals interconnect matrix RM0440 10.3.10 From system errors to timers (TIMx) and HRTIM TIMx (TIM1/TIM8/TIM20/TIM15/TIM16/TIM17) break inputs and HRTIM system fault input gather MCU internal fault events coming from: • the clock failure event generated by the clock security system (CSS), •...
Page 359: Table 73. Interconnect 16
RM0440 Peripherals interconnect matrix 10.3.11 From timers (TIM16/TIM17) to IRTIM Table 73. Interconnect 16 IRTIM control signal IRTIM control signals assignment modulation envelope signal tim16_oc1 carrier signal tim17_oc1 General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 32: Infrared interface (IRTIM).
Page 360 Direct memory access controller (DMA) RM0440 Direct memory access controller (DMA) 11.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 361: Table 74. Dma1 And Dma2 Implementation
DMA1 DMA2 Category 2 devices Number of channels Category 3 devices 1. See Table 1: STM32G4 Series memory density. 11.3.2 DMA request mapping The DMA controller is connected to DMA requests from the AHB/APB peripherals through the DMAMUX peripheral. For the mapping of the different requests, refer to the Section 12.3: DMAMUX...
Page 362: Figure 28. Dma Block Diagram
Direct memory access controller (DMA) RM0440 Figure 28. DMA block diagram DMA1 Ch 1 Ch 2 AHB master interface Ch 8 dma1_req [1..8] Arbiter dma1_ack [1..8] AHB slave Interrupt interface interface dma1_it[1..8] DMA2 Ch 1 Ch 2 AHB master interface Ch 8 dma2_req [1..8] Arbiter...
Page 363: Table 75. Dma Internal Input/Output Signals
RM0440 Direct memory access controller (DMA) According to its configuration through the AHB slave interface, the DMA controller arbitrates between the DMA channels and their associated received requests. The DMA controller also schedules the DMA data transfers over the single AHB port master. The DMA controller generates an interrupt per channel to the interrupt controller.
Page 364 Direct memory access controller (DMA) RM0440 address register. The start address used for the first transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register. • post-decrementing of the programmed DMA_CNDTRx register This register contains the remaining number of data items to transfer (number of AHB ‘read followed by write’...
Page 365 RM0440 Direct memory access controller (DMA) Pointer incrementation The peripheral and memory pointers may be automatically incremented after each transfer, depending on the PINC and MINC bits of the DMA_CCRx register. If the incremented mode is enabled (PINC or MINC set to 1), the address of the next transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data size defined in PSIZE[1:0] or MSIZE[1:0].
Page 366 Direct memory access controller (DMA) RM0440 Channel state and disabling a channel A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0).
Page 367 RM0440 Direct memory access controller (DMA) automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. In order to stop a circular transfer, the software needs to stop the peripheral from generating DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
Page 368 Direct memory access controller (DMA) RM0440 Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the destination peripheral in peripheral-to-peripheral mode. 368/2083 RM0440 Rev 1...
Page 369: Table 76. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1)
RM0440 Direct memory access controller (DMA) 11.4.6 DMA data width, alignment and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in Table Table 76. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination...
Page 370 Direct memory access controller (DMA) RM0440 Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:...
Page 371: Table 77. Dma Interrupt Requests
RM0440 Direct memory access controller (DMA) 11.5 DMA interrupts An interrupt can be generated on a half transfer, transfer complete or transfer error for each DMA channel x. Separate interrupt enable bits are available for flexibility. Table 77. DMA interrupt requests Interrupt Interrupt request Interrupt event...
Page 372 Direct memory access controller (DMA) RM0440 Bit 27 TEIF7: transfer error (TE) flag for channel 7 0: no TE event 1: a TE event occurred Bit 26 HTIF7: half transfer (HT) flag for channel 7 0: no HT event 1: a HT event occurred Bit 25 TCIF7: transfer complete (TC) flag for channel 7 0: no TC event 1: a TC event occurred...
Page 373 RM0440 Direct memory access controller (DMA) Bit 12 GIF4: global interrupt flag for channel 4 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 11 TEIF3: transfer error (TE) flag for channel 3 0: no TE event 1: a TE event occurred Bit 10 HTIF3: half transfer (HT) flag for channel 3...
Page 374 Direct memory access controller (DMA) RM0440 11.6.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx, HTIFx, TCIFx, in the DMA_ISR register.
Page 375 RM0440 Direct memory access controller (DMA) Bit 11 CTEIF3: transfer error flag clear for channel 3 Bit 10 CHTIF3: half transfer flag clear for channel 3 Bit 9 CTCIF3: transfer complete flag clear for channel 3 Bit 8 CGIF3: global interrupt flag clear for channel 3 Bit 7 CTEIF2: transfer error flag clear for channel 2 Bit 6 CHTIF2: half transfer flag clear for channel 2 Bit 5 CTCIF2: transfer complete flag clear for channel 2...
Page 376 Direct memory access controller (DMA) RM0440 Bits 11:10 MSIZE[1:0]: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.
Page 377 RM0440 Direct memory access controller (DMA) Bit 5 CIRC: circular mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 4 DIR: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
Page 378 Direct memory access controller (DMA) RM0440 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 8) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 379: Table 78. Dma Register Map And Reset Values
RM0440 Direct memory access controller (DMA) Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address.
Page 380 Direct memory access controller (DMA) RM0440 Table 78. DMA register map and reset values (continued) Offset Register DMA_IFCR 0x004 Reset value DMA_CCR1 0x008 Reset value DMA_CNDTR1 NDTR[15:0] 0x00C Reset value DMA_CPAR1 PA[31:0] 0x010 Reset value DMA_CMAR1 MA[31:0] 0x014 Reset value 0x018 Reserved Reserved.
Page 381 RM0440 Direct memory access controller (DMA) Table 78. DMA register map and reset values (continued) Offset Register DMA_CCR5 0x058 Reset value DMA_CNDTR5 NDTR[15:0] 0x05C Reset value DMA_CPAR5 PA[31:0] 0x060 Reset value DMA_CMAR5 MA[31:0] 0x064 Reset value 0x068 Reserved Reserved. DMA_CCR6 0x06C Reset value DMA_CNDTR6...
Page 382 DMA request multiplexer (DMAMUX) RM0440 DMA request multiplexer (DMAMUX) 12.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is de-asserted.
Page 383: Table 79. Dmamux Instantiation
Number of DMAMUX request generator channels Number of DMAMUX request trigger inputs Number of DMAMUX synchronization inputs Number of DMAMUX peripheral request inputs Table 1: STM32G4 Series memory density 12.3.2 DMAMUX mapping The mapping of resources to DMAMUX is hardwired.
Page 384: Table 80. Dmamux: Assignment Of Multiplexer Inputs To Resources
DMA request multiplexer (DMAMUX) RM0440 Table 80. DMAMUX: assignment of multiplexer inputs to resources request Resource request Resource request Resource MUX input MUX input MUX input DMAMUX_Req G0 TIM1_CH3 TIM20_CH2 DMAMUX_Req G1 TIM1_CH4 TIM20_CH3 DMAMUX_Req G2 TIM1_UP TIM20_CH4 DMAMUX_Req G3 TIM1_TRIG TIM20_UP ADC1...
Page 385: Table 82. Dmamux: Assignment Of Synchronization Inputs To Resources
RM0440 DMA request multiplexer (DMAMUX) Table 80. DMAMUX: assignment of multiplexer inputs to resources (continued) request Resource request Resource request Resource MUX input MUX input MUX input ADC2 TIM15_UP Reserved ADC3 TIM15_TRIG Reserved ADC4 TIM15_COM Reserved ADC5 TIM16_CH1 Reserved QUADSPI TIM16_UP Reserved DAC2_CH1...
Page 386 DMA request multiplexer (DMAMUX) RM0440 Table 82. DMAMUX: assignment of synchronization inputs to resources (continued) Sync. input Resource Sync. input Resource EXTI LINE5 Reserved EXTI LINE6 Reserved EXTI LINE7 Reserved EXTI LINE8 Reserved EXTI LINE9 Reserved EXTI LINE10 Reserved EXTI LINE11 Reserved EXTI LINE12 Reserved...
Page 387: Figure 29. Dmamux Block Diagram
RM0440 DMA request multiplexer (DMAMUX) 12.4 DMAMUX functional description 12.4.1 DMAMUX block diagram Figure 29 shows the DMAMUX block diagram. Figure 29. DMAMUX block diagram 32-bit AHB bus dmamux_hclk DMAMUX Request multiplexer AHB slave Channel m interface DMAMUX_CmCR Channel 1 Channel 0 DMA requests DMAMUX_C0CR...
Page 388: Table 83. Dmamux Signals
DMA request multiplexer (DMAMUX) RM0440 12.4.2 DMAMUX signals Table 83 lists the DMAMUX signals. Table 83. DMAMUX signals Signal name Description dmamux_hclk DMAMUX AHB clock dmamux_req_inx DMAMUX DMA request line inputs from peripherals dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block) dmamux_req_genx DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral...
Page 389 RM0440 DMA request multiplexer (DMAMUX) Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected. It is not allowed to configure a same non-null DMAREQ_ID to two different channels of the DMAMUX request line multiplexer. On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required.
Page 390: Figure 30. Synchronization Mode Of The Dmamux Request Line Multiplexer Channel
DMA request multiplexer (DMAMUX) RM0440 Figure 30. Synchronization mode of the DMAMUX request line multiplexer channel Selected DMA request line transferred to the output DMA requests served DMA request pending Selected dmamux_reqx Not pending dmamux_syncx dmamux_req_outx DMA request counter dmamux_evtx DMA request counter underrun Synchronization event DMA request counter auto-reload to NBREQ...
Page 391 RM0440 DMA request multiplexer (DMAMUX) Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request. Note: A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.
Page 392: Table 84. Dmamux Interrupts
DMA request multiplexer (DMAMUX) RM0440 Note: The GNBREQ field value shall only be written by software when the enable GE bit of the corresponding generator channel x is disabled. A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.
Page 393 RM0440 DMA request multiplexer (DMAMUX) 12.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX base address. DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address shall be aligned with the data size. 12.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
Page 394 DMA request multiplexer (DMAMUX) RM0440 Bit 7 Reserved, must be kept at reset value. Bits 6:0 DMAREQ_ID[6:0]: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 12.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) Address offset: 0x080 Reset value: 0x0000 0000...
Page 395 RM0440 DMA request multiplexer (DMAMUX) 12.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) Address offset: 0x100 + 0x04 * x (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] Res.
Page 396 DMA request multiplexer (DMAMUX) RM0440 12.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 397: Table 85. Dmamux Register Map And Reset Values
RM0440 DMA request multiplexer (DMAMUX) 12.6.7 DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. Table 85. DMAMUX register map and reset values Offset Register DMAREQ_ID[6:0]...
Page 398 DMA request multiplexer (DMAMUX) RM0440 Table 85. DMAMUX register map and reset values (continued) Offset Register DMAMUX_CSR 0x080 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_CCFR 0x084 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x088 - Reserved...
Page 399 RM0440 Nested vectored interrupt controller (NVIC) Nested vectored interrupt controller (NVIC) 13.1 NVIC main features ® • 102 maskable interrupt channels (not including the sixteen Cortex -M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 400: Table 86. Stm32G4 Series Vector Table
Nested vectored interrupt controller (NVIC) RM0440 13.3 Interrupt and exception vectors The gray rows in Table 86 describe the vectors without specific position. Table 86. STM32G4 Series vector table Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset...
Page 401 RM0440 Nested vectored interrupt controller (NVIC) Table 86. STM32G4 Series vector table (continued) Type of Acronym Description Address priority settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C settable DMA1_CH6 DMA1 channel 6 interrupt...
Page 402 Nested vectored interrupt controller (NVIC) RM0440 Table 86. STM32G4 Series vector table (continued) Type of Acronym Description Address priority TIM8_TRG_COM/TIM8 TIM8 trigger and commutation interrupt/TIM8 settable 0x0000 00F4 _DIR/TIM8_IDX Direction Change interrupt/TIM8 Index settable TIM1_CC TIM8 capture compare interrupt 0x0000 00F8...
Page 403 RM0440 Nested vectored interrupt controller (NVIC) Table 86. STM32G4 Series vector table (continued) Type of Acronym Description Address priority settable HRTIM_TIMF_IRQn hrtim_it7 / HRTIM timer F interrupt 0x0000 0168 settable CRS CRS interrupt 0x0000 016C settable SAI 0x0000 0170 TIM20_BRK/...
Page 404 Extended interrupts and events controller (EXTI) RM0440 Extended interrupts and events controller (EXTI) 14.1 Introduction The EXTI main features are as follows: • Generation of up to 42 event/interrupt requests – 28 configurable lines – 14 direct lines • Independent mask on each event/interrupt line •...
Page 405: Figure 32. Configurable Interrupt/Event Block Diagram
MS33393V1 14.3.2 Wakeup event management The STM32G4 Series is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex -M4 System Control register.
Page 406 Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR). Set the required bit of the software interrupt register (EXTI_SWIER). 14.4 EXTI interrupt/event line mapping In the STM32G4 Series, 42 interrupt/event lines are available. The GPIOs are connected to 16 configurable interrupt/event lines (see Figure 33).
Page 407: Table 87. Exti Lines Connections
RM0440 Extended interrupts and events controller (EXTI) Figure 33. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register PA15 PB15 PC15 EXTI15 PD15 PE15 PF15 MSv48953V1 The EXTI lines are connected as shown in Table 87: EXTI lines...
Page 408 Extended interrupts and events controller (EXTI) RM0440 Table 87. EXTI lines connections (continued) EXTI line Line source Line type COMP1 output configurable COMP2 output configurable I2C1 wakeup direct I2C2 wakeup direct USART1 wakeup direct USART2 wakeup direct I2C3 wakeup direct USART3 wakeup direct COMP3 output...
Page 409 RM0440 Extended interrupts and events controller (EXTI) 14.5 registers EXTI Refer to Section 1.2 on page 71 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 14.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: TBD IM31...
Page 410 Extended interrupts and events controller (EXTI) RM0440 14.5.3 Rising trigger selection register 1 (EXTI_RTSR1) Address offset: 0x08 Reset value: TBD RT31 RT30 RT29 Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 Res. RT17 RT16 RT15 RT14 RT13 RT12 RT11 RT10 Bits 31:29 RTx: Rising trigger event configuration bit of line x (x = 31 to 29)
Page 411 RM0440 Extended interrupts and events controller (EXTI) Bits 31:29 FTx: Falling trigger event configuration bit of line x (x = 31 to 29) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bits 28:23 Reserved, must be kept at reset value.
Page 412 Extended interrupts and events controller (EXTI) RM0440 Bits 22: 19 SWIx: Software interrupt on line x (x = 22 o 19) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
Page 413 RM0440 Extended interrupts and events controller (EXTI) 14.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined PIF31 PIF30 PIF29 Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 Res. PIF17 PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 414 Extended interrupts and events controller (EXTI) RM0440 Bits 31:12 Reserved, must be kept at reset value Bits 11:8 IMx: Interrupt mask on line x (x = 43 to 40) 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked Bits 7:6 Reserved, must be kept at reset value Bits 5:0 IMx: Interrupt mask on line x (x = 37 to 32) 0: Interrupt request from line x is masked...
Page 415 RM0440 Extended interrupts and events controller (EXTI) Bits 31:10 Reserved, must be kept at reset value. Bits 9:8 RTx: Rising trigger event configuration bit of line x (x = 40 to 41) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bits 7:2 Reserved, must be kept at reset value.
Page 416 Extended interrupts and events controller (EXTI) RM0440 14.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 417 RM0440 Extended interrupts and events controller (EXTI) Bits 31:10 Reserved, must be kept at reset value. Bits 9:8 SWIx: Software interrupt on line x (x = 40 to 41) If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt request generation.
Page 418: Table 88. Extended Interrupt/Event Controller Register Map And Reset Values
Extended interrupts and events controller (EXTI) RM0440 14.5.13 EXTI register map Table 88 gives the EXTI register map and the reset values. Table 88. Extended interrupt/event controller register map and reset values Offset Register EXTI_IMR1 0x00 Reset value EXTI_EMR1 0x04 Reset value EXTI_RTSR1 0x08...
Page 419 RM0440 Cyclic redundancy check calculation unit (CRC) Cyclic redundancy check calculation unit (CRC) 15.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 420: Table 89. Crc Internal Input/Output Signals
Cyclic redundancy check calculation unit (CRC) RM0440 15.3 CRC functional description 15.3.1 CRC block diagram Figure 34. CRC calculation unit block diagram 32-bit AHB bus 32-bit (read access) Data register (output) crc_hclk CRC computation 32-bit (write access) Data register (input) MS19882V2 15.3.2 CRC internal signals...
Page 421 RM0440 Cyclic redundancy check calculation unit (CRC) The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: •...
Page 422 Cyclic redundancy check calculation unit (CRC) RM0440 15.4 CRC registers 15.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 423 RM0440 Cyclic redundancy check calculation unit (CRC) 15.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 424: Table 90. Crc Register Map And Reset Values
Cyclic redundancy check calculation unit (CRC) RM0440 Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 15.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16] POL[15:0] Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation.
Page 425 RM0440 CORDIC co-processor (CORDIC) CORDIC co-processor (CORDIC) 16.1 CORDIC introduction The CORDIC co-processor provides hardware acceleration of certain mathematical functions (mainly trigonometric ones) commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, making it possible the use of a lower operating frequency, or freeing up processor cycles in order to perform other tasks.
Page 426: Table 91. Cordic Functions
CORDIC co-processor (CORDIC) RM0440 16.3 CORDIC functional description 16.3.1 General description The CORDIC is a cost-efficient successive approximation algorithm for evaluating trigonometric and hyperbolic functions. In trigonometric (circular) mode, the sine and cosine of an angle θ are determined by rotating the unit vector [1, 0] through decreasing angles until the cumulative sum of the rotation angles equals the input angle θ.
Page 427: Table 92. Cosine Parameters
RM0440 CORDIC co-processor (CORDIC) that only one operation is needed to obtain two values. This is the case, for example, when performing polar-to-rectangular conversion: sin θ also generates cos θ, while cos θ also generates sin θ. Similarly for rectangular-to-polar conversion (phase(x,y), modulus(x,y)) and for hyperbolic functions (cosh θ, sinh θ).
Page 428: Table 94. Phase Parameters
CORDIC co-processor (CORDIC) RM0440 The primary argument is the angle θ in radians. It must be divided by π before programming ARG1. The secondary argument m is the modulus, m. If m is greater than 1, a scaling must be applied in software to adapt it to the q1.31 range of ARG2.
Page 429: Table 96. Arctangent Parameters
RM0440 CORDIC co-processor (CORDIC) The primary argument is the x coordinate, that is, the magnitude of the vector in the direction of the x axis. If |x| > 1, a scaling must be applied in software to adapt it to the q1.31 range of ARG1.
Page 430: Table 97. Hyperbolic Cosine Parameters
CORDIC co-processor (CORDIC) RM0440 Hyperbolic cosine Table 97. Hyperbolic cosine parameters Parameter Description Range – ARG1 [-0.559 0.559] ⋅ ARG2 Not applicable – RES1 [0.5 0.846] ⋅ cosh – RES2 [-0.683 0.683] ⋅ sinh SCALE This function calculates the hyperbolic cosine of a hyperbolic angle x. It can also be used to calculate the exponential functions e = cosh x + sinh x, and e = cosh x - sinh x.
Page 431: Table 99. Hyperbolic Arctangent Parameters
RM0440 CORDIC co-processor (CORDIC) software, where n = 1. The scaled value x · 0.5 is programmed in ARG1 and the factor n = 1 must be programmed in the SCALE parameter. The secondary argument is not used. The primary result, RES1, is the hyperbolic sine, sinh x. RES1 must be multiplied by 2 to obtain the correct result.
Page 432: Table 101. Natural Log Scaling Factors And Corresponding Ranges
CORDIC co-processor (CORDIC) RM0440 value x · 2 is programmed in ARG1 and the factor n must be programmed in the SCALE parameter. Table 101 lists the valid scaling factors, n, and the corresponding ranges of x and ARG1. Table 101. Natural log scaling factors and corresponding ranges x range ARG1 range 0.107 ≤...
Page 433 RM0440 CORDIC co-processor (CORDIC) The primary result is the square root of x. RES1 must be multiplied by 2 to obtain the correct value. The secondary result is not used. 16.3.3 Fixed point representation The CORDIC operates in fixed point signed integer format. Input and output values can be either q1.31 or q1.15.
Page 434: Figure 35. Cordic Convergence For Trigonometric Functions
CORDIC co-processor (CORDIC) RM0440 Figure 35. CORDIC convergence for trigonometric functions 434/2083 RM0440 Rev 1...
Page 435: Figure 36. Cordic Convergence For Hyperbolic Functions
RM0440 CORDIC co-processor (CORDIC) Figure 36. CORDIC convergence for hyperbolic functions RM0440 Rev 1 435/2083...
Page 436: Table 104. Precision Vs. Number Of Iterations
CORDIC co-processor (CORDIC) RM0440 Figure 37. CORDIC convergence for square root Note: The convergence rate decreases as the quantization error starts to become significant. The CORDIC can perform four iterations per clock cycle. For each function, the maximum error remaining after every four iterations is shown in Table 104, together with the number of clock cycles required to reach that precision.
Page 437 RM0440 CORDIC co-processor (CORDIC) Table 104. Precision vs. number of iterations (continued) Max residual error Number of Number of Function iterations cycles q1.31 format q1.15 format Sinh, Cosh, Atanh, Ln Sqrt 1. Max residual error is the maximum error remaining after the given number of iterations, compared to the identical calculation performed in double precision floating point.
Page 438 CORDIC co-processor (CORDIC) RM0440 Once the calculation has started, any attempt to read the CORDIC_RDATA register will insert bus wait states until the calculation has finished, before returning the result. Hence it is possible for the software to write the input and immediately read the result without polling to see if it is valid.
Page 439 RM0440 CORDIC co-processor (CORDIC) 16.3.8 Interrupt mode By setting the interrupt enable (IE) bit in the CORDIC_CSR register, an interrupt will be generated whenever the RRDY flag is set. The interrupt is cleared when the flag is reset. This mode allows the result of the calculation to be read under interrupt service routine, and hence given a priority relative to other tasks.
Page 440 CORDIC co-processor (CORDIC) RM0440 Note: Each DMA request must be acknowledged, as a result of the DMA performing an access to the CORDIC_WDATA or CORDIC_RDATA register. If an extraneous access to the relevant register occurs before this, the acknowledge will be asserted prematurely, and could block the DMA channel.
Page 441 RM0440 CORDIC co-processor (CORDIC) 16.4 CORDIC registers Note: The CORDIC registers may only be accessed in 32-bit word format 16.4.1 CORDIC control/status register (CORDIC_CSR) Address offset: 0x00 Reset value: 0x0000 0050 NARG RRDY Res. Res. Res. Res. Res. Res. Res. Res.
Page 442 CORDIC co-processor (CORDIC) RM0440 Bit 19 NRES: Number of results in the CORDIC_RDATA register. 0: Only one 32-bit value (or two 16-bit values if RESSIZE = 1) will be transferred to the CORDIC_RDATA register on completion of the next calculation. One read from CORDIC_RDATA will reset the RRDY flag.
Page 443 RM0440 CORDIC co-processor (CORDIC) 16.4.2 CORDIC argument register (CORDIC_WDATA) Address offset: 0x04 Reset value: N/A ARG[31:16] ARG[15:0] Bits 31:0 ARG: Function input arguments This register is programmed with the input arguments for the function selected in the CORDIC_CSR register FUNC field. If 32-bit format is selected (CORDIC_CSR.ARGSIZE = 0) and two input arguments are required (CORDIC_CSR.NARGS = 1), two successive writes are required to this register.
Page 444 CORDIC co-processor (CORDIC) RM0440 16.4.3 CORDIC result register (CORDIC_RDATA) Address offset: 0x8 Reset value: 0x0000 0000 RES[31:16] RES[15:0] Bits 31:0 RES: Function result If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag is set.
Page 445: Table 105. Cordic Register Map
RM0440 CORDIC co-processor (CORDIC) 16.4.4 CORDIC register map Table 105 summarizes the CORDIC registers. Table 105. CORDIC register map Register size Register name Offset reset value CORDIC_CSR SCALE PRECISION FUNC 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 CORDIC_WDATA 0x04...
Page 446 Filter Math Accelerator (FMAC) RM0440 Filter Math Accelerator (FMAC) 17.1 FMAC introduction The filter math accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented.
Page 447: Figure 38. Block Diagram
RM0440 Filter Math Accelerator (FMAC) 17.3 FMAC functional description 17.3.1 General description The FMAC is shown in Figure Figure 38. Block diagram Control and sequencing Read x1, x2 pointer offset pointers Write y offset pointers pointers Buffer base address Local pointers Memory Multiply and...
Page 448 Filter Math Accelerator (FMAC) RM0440 17.3.2 Local memory and buffers The unit contains a 256 x 16-bit read/write memory which is used for local storage. • Input values (the elements of the input vectors) are stored in two buffers, X1 and X2. •...
Page 449: Figure 39. Input Buffer Areas
RM0440 Filter Math Accelerator (FMAC) Figure 39. Input buffer areas X1 buffer X2 buffer x1_buf_size x2_buf_size MSv45869V1 The X1 buffer can be used as a circular buffer, in which case new data are continually transferred into the input buffer whenever space is available. Pre-loading this buffer is optional for digital filters, since if no input samples have been written in the buffer when the operation is started, it is flagged as empty, which will trigger the CPU or DMA to load new samples until there are enough to begin operation.
Page 450: Figure 40. Circular Input Buffer
Filter Math Accelerator (FMAC) RM0440 Figure 40. Circular input buffer x1_base Available buffer space x[n-N] x[n-6] x[n-5] These values in use for calculating y[n] x[n-4] x[n-3] x[n-2] x[n-1] x[n] x[n+1] x[n+2] Next values already loaded x[n+3] x[n+4] Write pointer Available buffer space MSv45870V1 The X2 buffer can only be used in vector mode (ie.
Page 451: Figure 41. Circular Input Buffer Operation
RM0440 Filter Math Accelerator (FMAC) Note: If the flow of samples is controlled by a timer or other peripheral such as an ADC, the buffer will regularly go empty, since the filter processes each new sample faster than the source can provide it.
Page 452: Figure 42. Circular Output Buffer
Filter Math Accelerator (FMAC) RM0440 Figure 42. Circular output buffer y_base Available buffer space Read pointer y[n-M-4] y[n-M-3] These samples not yet read y[n-M-2] y[n-M-1] y[n-M] y[n-6] These samples in use y[n-5] for calculating y[n] y[n-4] y[n-3] y[n-2] y[n-1] Next sample y[n] Available buffer space MSv45873V1...
Page 453: Figure 43. Circular Output Buffer Operation
RM0440 Filter Math Accelerator (FMAC) Figure 43. Circular output buffer operation y[n-7] y[n-8] y[n-6] y[n-7] y[n-7] y[n-7] Read pointer y[n-5] y[n-6] y[n-6] y[n-6] y[n-4] y[n-5] y[n-5] y[n-5] y[n-3] y[n-4] y[n-4] y[n-4] y[n-2] y[n-3] y[n-3] y[n-3] Read pointer y[n-1] y[n-2] y[n-2] y[n-2] Next sample y[n]...
Page 454 Filter Math Accelerator (FMAC) RM0440 Load X2 buffer This function pre-loads the X2 buffer with N + M values, starting from the address in X2_BASE. Successive writes to the FMAC_WDATA register will load the write data into the X2 buffer and increment the write address. The function can be used to pre-load the buffer with the elements of a vector, or the coefficients of a filter.
Page 455: Figure 44. Fir Filter Structure
RM0440 Filter Math Accelerator (FMAC) = B.X , where X = [x ,...,x ] is composed of the N+1 elements of X at indices n - N to This function corresponds to a finite impulse response (FIR) filter, where vector B contains the filter coefficients and vector X the sampled data.
Page 456 Filter Math Accelerator (FMAC) RM0440 Parameters: • The parameter P contains the length, N+1, of the coefficient vector B in the range [2:127]. • The parameter R contains the gain to be applied to the accumulator output. The value output to the Y buffer is multiplied by 2 , where R is in the range [0:7] •...
Page 457: Figure 45. Iir Filter Structure (Direct Form 1)
RM0440 Filter Math Accelerator (FMAC) Figure 45. IIR filter structure (direct form 1) b[0] x[n] y[n] b[1] a[1] x[n-1] y[n-1] b[2] a[2] x[n-2] y[n-2] b[3] a[3] x[n-3] y[n-3] b[N] a[M] x[n-N] y[n-M] MSv47127V1 Input: • X1 buffer contains the elements of vector X. It is a circular buffer of length N + 1+ d. •...
Page 458 Filter Math Accelerator (FMAC) RM0440 The function completes when the START bit in the FMAC_PARAM register is reset by software. 17.3.7 Fixed point representation The FMAC operates in fixed point signed integer format. Input and output values are q1.15. In q1.15 format, numbers are represented by one sign bit and 15 fractional bits (binary decimal places).
Page 459: Table 106. Valid Combinations For Read And Write Methods
RM0440 Filter Math Accelerator (FMAC) However, if the memory space is limited, the X1 and Y buffer areas can be overlapped, such that each output sample takes the place of the oldest input sample, which is no longer required: • X2_BASE = 0;...
Page 460 Filter Math Accelerator (FMAC) RM0440 Table 106. Valid combinations for read and write methods (continued) WIEN RIEN DMAWEN DMAREN Write Read Interrupt Interrupt The filter is started by writing to the FMAC_PARAM register with the following bit-field values: – FUNC = 8 (FIR filter); –...
Page 461 RM0440 Filter Math Accelerator (FMAC) As for the FIR, for maximum throughput a small amount of additional space, d1 and d2, should be allowed in the input and output buffer size respectively, making the total memory requirement 2M + 2N + d1 + d2. The buffers should be configured as follows: –...
Page 462: Figure 46. X1 Buffer Initialisation
Filter Math Accelerator (FMAC) RM0440 EMPTY_WM When new output samples have been written into the Y buffer, the YEMPTY flag in the FMAC_SR register will go low. If the RIEN bit is set in the FMAC_CR register, the EMPTY_WM interrupt request will be asserted to request the processor to read samples from the buffer, via the FMAC_RDATA register.
Page 463: Figure 47. Filtering Example 1
RM0440 Filter Math Accelerator (FMAC) 17.3.11 Examples of filter operation Figure 47. Filtering example 1 FMAC_WDATA FMAC_RDATA FMAC_WDATA FMAC_WDATA FMAC_WDATA register write: register read: register write: register write: register write: WDATA = x[4] RDATA = y[0] WDATA = x[7] WDATA = x[8] WDATA = x[9] FMAC_PARAM register write:...
Page 464: Figure 48. Filtering Example 2
Filter Math Accelerator (FMAC) RM0440 filter length is small and the processor relatively slow, in this example. So increasing the Y buffer size would not help. Figure 48. Filtering example 2 FMAC_WDATA FMAC_RDATA FMAC_RDATA register write: register read: register read: WDATA = x[4] RDATA = y[0] RDATA = y[1]...
Page 465 RM0440 Filter Math Accelerator (FMAC) 17.3.12 Filter design tips The FMAC architecture imposes some constraints on the design of digital filters. Implementation of direct form 2, or transposed forms, is not efficient. Filters which have been designed for such forms should be converted to direct form 1. Cascaded filters must either be combined into a single stage, or implemented as separate filters.
Page 466 Filter Math Accelerator (FMAC) RM0440 17.4 FMAC registers 17.4.1 FMAC X1 Buffer Configuration register (FMAC_X1BUFCFG) Address offset: 0x00 Reset value: 0x0000 0000 This register can only be modified if START = 0 in the FMAC_PARAM register. Res. Res. Res. Res. Res.
Page 467 RM0440 Filter Math Accelerator (FMAC) Bits 31:16 Reserved Bits 15:8 X2_BUF_SIZE: Size of X2 buffer in 16-bit words. This field can not be modified when a function is ongoing (START = 1) Bits 7:0 X2_BASE: Base address of X2 buffer. The X2 buffer base address can be modified while START=1, for example to change coefficient values.
Page 468 Filter Math Accelerator (FMAC) RM0440 17.4.4 FMAC Parameter register (FMAC_PARAM) Address offset: 0x0C Reset value: 0x0000 0000 START FUNC Bit 31 START: Enable execution 0: Stop execution 1: Start execution Setting this bit will trigger the execution of the function selected in the FUNC field. Resetting it by software will stop any ongoing function.
Page 469 RM0440 Filter Math Accelerator (FMAC) 17.4.5 FMAC Control register (FMAC_CR) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RESET CLIP UNFL OVFL Res. Res. Res. Res. Res. Res.
Page 470 Filter Math Accelerator (FMAC) RM0440 Bit 2 OVFLIEN: Enable overflow error interrupts. 0: Disabled. No interrupt will be generated upon overflow detection. 1: Enabled. An interrupt request will be generated if the OVFL flag is set This bit is set and cleared by software. A read returns the current state of the bit. Bit 1 WIEN: Enable write interrupt.
Page 471 RM0440 Filter Math Accelerator (FMAC) Bits 7:2 Reserved Bit 1 X1FULL: X1 buffer full flag. The buffer is flagged as full if the number of available spaces is less than the FULL_WM threshold. The number of available spaces is the difference between the write pointer and the least recent sample currently in use.
Page 472 Filter Math Accelerator (FMAC) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDATA[15:0] Bits 31:16 Reserved Bits 15:0 RDATA: Read data. When a read access to this register occurs, the read data are the contents of the Y output buffer at the address offset indicated by the READ pointer.
Page 473: Table 107. Fmac Register Map
RM0440 Filter Math Accelerator (FMAC) 17.4.9 FMAC register map Table 107 summarizes the FMAC registers. Table 107. FMAC register map Register size Register name Offset reset value FMAC_X1BUFCFG Reserved Reserved X1_BUF_SIZE[7:0] X1_BASE[7:0] 0x00 Reset value 0 0 0 FMAC_X2BUFCFG Reserved X2_BUF_SIZE[7:0] X2_BASE[7:0] 0x04...
Page 474 Flexible memory controller (FMC) RM0440 Flexible memory controller (FMC) The Flexible memory controller (FMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller 18.1 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static memories, and NAND Flash memory.
Page 475: Figure 49. Fmc Block Diagram
RM0440 Flexible memory controller (FMC) The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time. 18.2 FMC block diagram The FMC consists of the following main blocks:...
Page 476 Flexible memory controller (FMC) RM0440 18.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 477 RM0440 Flexible memory controller (FMC) to any other value than 0, the FMC chip select (FMC_NEx) toggles between the consecutive accesses. This feature is required when interfacing with FRAM memory. • AHB transaction size is smaller than the memory size: The transfer may or not be consistent depending on the type of external device: –...
Page 478: Table 108. Nor/Psram Bank Selection
Flexible memory controller (FMC) RM0440 Figure 50. FMC memory banks Supported memory type Address Bank 0x6000 0000 Bank 1 NOR/PSRAM/SRAM 4 x 64 Mbyte 0x6FFF FFFF 0x7000 0000 Not used 0x7FFF FFFF 0x8000 0000 Bank 3 NAND Flash memory 4 x 64 Mbyte 0x8FFF FFFF 0x9000 0000 Not used...
Page 479: Table 110. Nand Memory Mapping And Timing Registers
RM0440 Flexible memory controller (FMC) 1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. 18.4.2 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in...
Page 480 Flexible memory controller (FMC) RM0440 18.5 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • Asynchronous SRAM, FRAM and ROM – 8 bits – 16 bits • PSRAM (CellularRAM™) – Asynchronous mode –...
Page 481: Table 112. Programmable Nor/Psram Access Parameters
RM0440 Flexible memory controller (FMC) Table 112. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address Duration of the address AHB clock cycle Asynchronous setup setup phase (HCLK) Duration of the address hold Asynchronous, AHB clock cycle Address hold phase muxed I/Os...
Page 482: Table 114. 16-Bit Multiplexed I/O Nor Flash Memory
Flexible memory controller (FMC) RM0440 NOR Flash memory, 16-bit multiplexed I/Os Table 114. 16-bit multiplexed I/O NOR Flash memory FMC signal name Function Clock (for synchronous access) A[25:16] Address bus 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] Chip select, x = 1..4 Output enable...
Page 483: Table 117. Nor Flash/Psram: Example Of Supported Memories And Transactions
RM0440 Flexible memory controller (FMC) Table 116. 16-Bit multiplexed I/O PSRAM (continued) FMC signal name I/O Function NE[x] Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FMC NBL[1:0]...
Page 484 Flexible memory controller (FMC) RM0440 Table 117. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Use of byte lanes NBL[1:0] Asynchronous Asynchronous Asynchronous Split into 2 FMC accesses PSRAM Asynchronous Split into 2 FMC accesses...
Page 485: Figure 51. Mode1 Read Access Waveforms
RM0440 Flexible memory controller (FMC) 18.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM, FRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) •...
Page 486: Table 118. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0440 Figure 52. Mode1 write access waveforms Memory transaction A[25:0] NBL[x:0] Data bus Data driven by controller NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles cycles MSv41665V1 The DATAHLD time at the end of the read and write transactions guarantee the address and data hold time after the NOE/NWE rising edge.
Page 487: Table 119. Fmc_Btrx Bit Fields
RM0440 Flexible memory controller (FMC) Table 118. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP As needed, exclude 0x2 (NOR Flash memory) MUXE MBKEN Table 119. FMC_BTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30 DATAHLD...
Page 488: Table 120. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0440 Figure 54. ModeA write access waveforms Memory transaction A[25:0] NBL[x:0] Data bus Data driven by controller NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles cycles MSv41665V1 The differences compared with Mode1 are the toggling of NOE and the independent read and write timings.
Page 489: Table 121. Fmc_Btrx Bit Fields
RM0440 Flexible memory controller (FMC) Table 120. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP As needed, exclude 0x2 (NOR Flash memory) MUXEN MBKEN Table 121. FMC_BTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30 DATAHLD...
Page 490: Figure 55. Mode2 And Mode B Read Access Waveforms
Flexible memory controller (FMC) RM0440 Mode 2/B - NOR Flash Figure 55. Mode2 and mode B read access waveforms Memory transaction A[25:0] NADV High D[15:0] Data driven by memory ADDSET HCLK cycles DATAST HCLK cycles DATAHLD HCLK cycles MSv41678V1 Figure 56. Mode2 write access waveforms Memory transaction A[25:0] NADV...
Page 491: Table 123. Fmc_Bcrx Bit Fields
RM0440 Flexible memory controller (FMC) Figure 57. ModeB write access waveforms Memory transaction A[25:0] NADV Data bus Data driven by controller ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK cycles MSv41680V1 The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B).
Page 492: Table 124. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0440 Table 123. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) MUXEN MBKEN Table 124. FMC_BTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30 DATAHLD accesses and DATAHLD+1 HCLK cycles for write accesses when...
Page 493: Figure 58. Modec Read Access Waveforms
RM0440 Flexible memory controller (FMC) Mode C - NOR Flash - OE toggling Figure 58. ModeC read access waveforms Memory transaction A[25:0] NADV High D[15:0] Data driven by memory ADDSET HCLK cycles DATAST HCLK cycles DATAHLD HCLK cycles MSv41682V1 Figure 59. ModeC write access waveforms Memory transaction A[25:0] NADV...
Page 494: Table 126. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0440 Table 126. FMC_BCRx bit fields Bit number Bit name Value to set 31:24 Reserved 0x000 23:22 NBLSET[1:0] Don’t care CCLKEN As needed CBURSTRW 0x0 (no effect in Asynchronous mode) 18:16 CPSIZE 0x0 (no effect in Asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature.
Page 495: Table 128. Fmc_Bwtrx Bit Fields
RM0440 Flexible memory controller (FMC) Table 128. FMC_BWTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD+1 HCLK cycles for write 31:30 DATAHLD accesses). 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Page 496: Table 129. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0440 Figure 61. ModeD write access waveforms Memory transaction A[25:0] NADV NBL[x:0] Data bus Data driven by controller NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles HCLK cycles cycles MSv41684V1 The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.
Page 497: Table 130. Fmc_Btrx Bit Fields
RM0440 Flexible memory controller (FMC) Table 129. FMC_BCRx bit fields (continued) Bit number Bit name Value to set FACCEN Set according to memory support MWID As needed MTYP As needed MUXEN MBKEN Table 130. FMC_BTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30...
Page 498: Figure 62. Muxed Read Access Waveforms
Flexible memory controller (FMC) RM0440 Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 62. Muxed read access waveforms Memory transaction A[25:16] NADV NBL[x:0] High AD[15:0] Lower address Data driven by memory NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD HCLK HCLK...
Page 499: Table 132. Fmc_Bcrx Bit Fields
RM0440 Flexible memory controller (FMC) Figure 63. Muxed write access waveforms Memory transaction A[25:16] NADV NBL[x:0] AD[15:0] Lower address Data driven by controller NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles HCLK cycles cycles MSv41686V1 The difference with ModeD is the drive of the lower address byte(s) on the data bus.
Page 500: Table 133. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0440 Table 132. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MWID As needed MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 133. FMC_BTRx bit fields Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30 DATAHLD...
Page 501: Figure 64. Asynchronous Wait During A Read Access Waveforms
RM0440 Flexible memory controller (FMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: – –...
Page 502: Figure 65. Asynchronous Wait During A Write Access Waveforms
Flexible memory controller (FMC) RM0440 Figure 65. Asynchronous wait during a write access waveforms Memory transaction A[25:0] address phase data setup phase NWAIT don’t care don’t care 1HCLK D[15:0] data driven by FMC 3HCLK MSv40168V1 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. CellularRAM™...
Page 503 RM0440 Flexible memory controller (FMC) register. The FMC does not include the clock cycle when NADV is low in the data latency count. Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: •...
Page 504: Figure 66. Wait Configuration Waveforms
Flexible memory controller (FMC) RM0440 The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3). Figure 66. Wait configuration waveforms Memory transaction = burst of 4 half words HCLK addr[25:16] A[25:16]...
Page 505: Table 134. Fmc_Bcrx Bit Fields
RM0440 Flexible memory controller (FMC) Figure 67. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG= (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data data...
Page 506: Table 135. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0440 Table 134. FMC_BCRx bit fields (continued) Bit number Bit name Value to set WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN As needed...
Page 507: Table 136. Fmc_Bcrx Bit Fields
RM0440 Flexible memory controller (FMC) Figure 68. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) Memory transaction = burst of 2 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 508: Table 137. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0440 Table 136. FMC_BCRx bit fields (continued) Bit number Bit name Value to set WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP...
Page 509 RM0440 Flexible memory controller (FMC) 18.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control register for bank x (FMC_BCRx) (x = 1 to Address offset: 8 * (x – 1), (x = 1 to 4) Reset value: Bank 1: 0x0000 30DB Reset value: Bank 2: 0x0000 30D2 Reset value: Bank 3: 0x0000 30D2 Reset value: Bank 4: 0x0000 30D2 This register contains the control information of each memory bank, used for SRAMs,...
Page 510 Flexible memory controller (FMC) RM0440 Bit 20 CCLKEN: Continuous Clock Enable. This bit enables the FMC_CLK clock output to external memory devices. 0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset).
Page 511 RM0440 Flexible memory controller (FMC) Bit 13 WAITEN: Wait enable bit. This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)
Page 512 Flexible memory controller (FMC) RM0440 Bits 3:2 MTYP[1:0]: Memory type. Defines the type of external memory attached to the corresponding memory bank: 00: SRAM/FRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) / FRAM 10: NOR Flash/OneNAND Flash (default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit.
Page 513 RM0440 Flexible memory controller (FMC) Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: Access mode A 01: Access mode B 10: Access mode C 11: Access mode D...
Page 514 Flexible memory controller (FMC) RM0440 Bits 15:8 DATAST[7:0]: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 51 Figure 63), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 ×...
Page 515 RM0440 Flexible memory controller (FMC) SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) Address offset: 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories.
Page 516 Flexible memory controller (FMC) RM0440 Bits 15:8 DATAST[7:0]: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 51 Figure 63), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 ×...
Page 517: Table 138. Programmable Nand Flash Access Parameters
RM0440 Flexible memory controller (FMC) Bits 31:20 Reserved, must be kept at reset value. Bit 19 CNTB4EN: Counter Bank 4 enable This bit enables the chip select counter for PSRAM/NOR Bank 4. 0: Counter disabled for Bank 4 1: Counter enabled for Bank 4 Bit 18 CNTB3EN: Counter Bank 3 enable This bit enables the chip select counter for PSRAM/NOR Bank 3.
Page 518: Table 139. 8-Bit Nand Flash
Flexible memory controller (FMC) RM0440 Table 138. Programmable NAND Flash access parameters (continued) Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) during which the address must be AHB clock cycle Memory hold held (as well as the data if a write Read/Write (HCLK) access is performed) after the...
Page 519: Table 140. 16-Bit Nand Flash
RM0440 Flexible memory controller (FMC) 16-bit NAND Flash memory Table 140. 16-bit NAND Flash FMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus Chip select NOE(= NRE) Output enable (memory signal name: read enable, NRE)
Page 520: Table 141. Supported Memories And Transactions
Flexible memory controller (FMC) RM0440 18.6.2 NAND Flash supported memories and transactions Table 141 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 141. Supported memories and transactions Memory Allowed/ Device...
Page 521: Figure 69. Nand Flash Controller Waveforms For Common Memory Access
RM0440 Flexible memory controller (FMC) Figure 69. NAND Flash controller waveforms for common memory access HCLK A[25:0] NCEx High NREG, NIOW, NIOR MEMxSET MEMxHOLD MEMxWAIT + 1 NWE, MEMxHIZ + 1 write_data read_data Valid MS33733V3 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2.
Page 522: Figure 70. Access To Non 'Ce Don't Care' Nand-Flash
Flexible memory controller (FMC) RM0440 to implement the prewait functionality needed by some NAND Flash memories (see details in Section 18.6.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank.
Page 523 RM0440 Flexible memory controller (FMC) When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 524 Flexible memory controller (FMC) RM0440 To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR register and store it in a variable. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page.
Page 525 RM0440 Flexible memory controller (FMC) Bits 12:9 TCLR[3:0]: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space.
Page 526 Flexible memory controller (FMC) RM0440 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN Bits 31:7 Reserved, must be kept at reset value. Bit 6 FEMPT: FIFO empty.
Page 527 RM0440 Flexible memory controller (FMC) MEMHIZ[7:0] MEMHOLD[7:0] MEMWAIT[7:0] MEMSET[7:0] Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 528 Flexible memory controller (FMC) RM0440 ATTHIZ[7:0] ATTHOLD[7:0] ATTWAIT[7:0] ATTSET[7:0] Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 529: Table 142. Ecc Result Relevant Bits
RM0440 Flexible memory controller (FMC) ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 18.6.6: Computation of the error correction code (ECC) in NAND Flash...
Page 530: Table 143. Fmc Register Map
Flexible memory controller (FMC) RM0440 18.7 FMC register map Table 143. FMC register map Offset Register CPSIZE MWID MTYP FMC_BCR1 [2:0] [1:0] [1:0] 0x00 [1:0] Reset value CPSIZE MWID MTYP FMC_BCR2 [2:0] [1:0] [1:0] 0x08 [1:0] Reset value CPSIZE MWID MTYP FMC_BCR3 [2:0]...
Page 531 RM0440 Flexible memory controller (FMC) Table 143. FMC register map (continued) Offset Register FMC_BWTR1 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x104 Reset value FMC_BWTR2 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x10C Reset value FMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value FMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x11C Reset value...
Page 532: Figure 71. Quadspi Block Diagram When Dual-Flash Mode Is Disabled
Quad-SPI interface (QUADSPI) RM0440 Quad-SPI interface (QUADSPI) 19.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 533: Table 144. Quadspi Pins
RM0440 Quad-SPI interface (QUADSPI) Figure 72. QUADSPI block diagram when dual-flash mode is enabled QUADSPI Registers / Clock control management SPI FLASH 1 BK1_IO0/SO Q0/SI BK1_IO1/SI Q1/SO BK1_IO2 FIFO Q2/WP BK1_IO3 Q3/HOLD BK1_nCS SPI FLASH 2 Shift register BK2_IO0/SO Q0/SI BK2_IO1/SI Q1/SO BK2_IO2...
Page 534: Figure 73. An Example Of A Read Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0440 19.3.3 QUADSPI command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
Page 535 RM0440 Quad-SPI interface (QUADSPI) Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
Page 536 Quad-SPI interface (QUADSPI) RM0440 mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.
Page 537: Figure 74. An Example Of A Ddr Command In Quad Mode
RM0440 Quad-SPI interface (QUADSPI) SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge.
Page 538 Quad-SPI interface (QUADSPI) RM0440 The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2.
Page 539 RM0440 Quad-SPI interface (QUADSPI) is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command.
Page 540 Quad-SPI interface (QUADSPI) RM0440 The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written.
Page 541 RM0440 Quad-SPI interface (QUADSPI) that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled.
Page 542 Quad-SPI interface (QUADSPI) RM0440 DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode. The DMA requests are enabled setting the DMAEN bit.
Page 543 RM0440 Quad-SPI interface (QUADSPI) When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) •...
Page 544 Quad-SPI interface (QUADSPI) RM0440 In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses.
Page 545: Figure 75. Ncs When Ckmode = 0 (T = Clk Period)
RM0440 Quad-SPI interface (QUADSPI) 19.3.14 QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty.
Page 546: Figure 77. Ncs When Ckmode = 1 In Ddr Mode (T = Clk Period)
Quad-SPI interface (QUADSPI) RM0440 When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 77.
Page 547: Table 145. Quadspi Interrupt Requests
RM0440 Quad-SPI interface (QUADSPI) 19.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 145. QUADSPI interrupt requests Interrupt event Event flag Enable control bit...
Page 548 Quad-SPI interface (QUADSPI) RM0440 19.5 QUADSPI registers 19.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER[7:0] APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. Res. FTHRES[3:0] FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31:24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the clock (value+1).
Page 549 RM0440 Quad-SPI interface (QUADSPI) Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
Page 550 Quad-SPI interface (QUADSPI) RM0440 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays.
Page 551 RM0440 Quad-SPI interface (QUADSPI) 19.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE[4:0] Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. Res.
Page 552 Quad-SPI interface (QUADSPI) RM0440 19.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[4:0] Res. Res. BUSY Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 FLEVEL[4:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO.
Page 553 RM0440 Quad-SPI interface (QUADSPI) 19.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 554 Quad-SPI interface (QUADSPI) RM0440 Bits 31:0 DL[31:0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE.
Page 555 RM0440 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode Section 19.3.12: Sending the instruction only once on page 544. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 556 Quad-SPI interface (QUADSPI) RM0440 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 557 RM0440 Quad-SPI interface (QUADSPI) 19.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31:0 ALTERNATE[31:0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 19.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020...
Page 558 Quad-SPI interface (QUADSPI) RM0440 19.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31:0 MASK[31:0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is...
Page 559 RM0440 Quad-SPI interface (QUADSPI) 19.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INTERVAL[15:0]: Polling interval Number of CLK cycles between to read during automatic polling phases.
Page 560: Table 146. Quadspi Register Map And Reset Values
Quad-SPI interface (QUADSPI) RM0440 19.5.14 QUADSPI register map Table 146. QUADSPI register map and reset values Register Offset name FTHRES QUADSPI_CR PRESCALER[7:0] [3:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[5:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 561 RM0440 Analog-to-digital converters (ADC) Analog-to-digital converters (ADC) 20.1 Introduction This section describes the implementation of up to 5 ADCs: • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 and ADC4 are tightly coupled and can operate in dual mode (ADC3 is master). •...
Page 562 Analog-to-digital converters (ADC) RM0440 20.2 ADC main features • High-performance features – Up to 5 ADCs, out of which four of them ((in pairs) can operate in dual mode: ADC1 is connected to 14 external channels + 4 internal channels ADC2 is connected to 16 external channels + 2 internal channels ADC3 is connected to 15 external channels + 3 internal channels ADC4 is connected to 16 external channels + 2 internal channels...
Page 563: Table 147. Main Adc Features
RM0440 Analog-to-digital converters (ADC) • Low-power features – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency – Allows slow bus frequency application while keeping optimum ADC performance – Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode) •...
Page 564: Figure 79. Adc Block Diagram
Analog-to-digital converters (ADC) RM0440 20.4 ADC functional description 20.4.1 ADC block diagram Figure 79 shows the ADC block diagram and Table 149 gives the ADC pin description. Figure 79. ADC block diagram REF+ 1.62 to 3.6 V AREADY EOSMP adc_it Analog Supply (VDDA) SWTRIG 1.62V to 3.6 V...
Page 565: Table 148. Adc Internal Input/Output Signals
RM0440 Analog-to-digital converters (ADC) 20.4.2 ADC pins and internal signals Table 148. ADC internal input/output signals Signal Internal signal name Description type Up to 32 external trigger inputs for the regular conversions (can be connected to on-chip timers). adc_ext_trg[31:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 566 Analog-to-digital converters (ADC) RM0440 20.4.3 Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 80: ADC clock scheme):...
Page 567 RM0440 Analog-to-digital converters (ADC) Figure 80. ADC clock scheme (ADC1, ADC2) or (ADC3, ADC4, ADC5) (Reset and clock adc_hclk AHB interface controller) Bits CKMODE[1:0] of ADCx_CCR Analog ADC1 or 3 (master) /1 or /2 or /4 Others Analog ADC2 or 4 (slave) /1, 2, 4, 6, 8, 10, adc_ker_ck...
Page 568: Figure 81. Adc1 Connectivity
Analog-to-digital converters (ADC) RM0440 20.4.4 ADC1/2/3/4/5 connectivity ADC1, ADC2, ADC3, ADC4 and ADC5 are tightly coupled and share some external channels as described in the below figures. Figure 81. ADC1 connectivity ADC1 Channel selection Fast channel ADC12_INP1 Fast channel ADC12_INN1 ADC12_INP2 Fast channel ADC1_INN2...
Page 569: Figure 82. Adc2 Connectivity
RM0440 Analog-to-digital converters (ADC) Figure 82. ADC2 connectivity ADC2 Channel selection Fast channel ADC12_INP1 Fast channel ADC12_INN1 ADC12_INP2 Fast channel ADC2_INN2 ADC2_INP3 Fast channel ADC2_INN3 ADC2_INP4 Fast channel ADC2_INN4 ADC2_INP5 Fast channel ADC12_INN5 ADC12_INP6 Slow channel ADC12_INN6 REF+ ADC12_INP7 Slow channel ADC12_INN7 ADC12_INP8 Slow channel...
Page 570: Figure 83. Adc3 Connectivity
Analog-to-digital converters (ADC) RM0440 Figure 83. ADC3 connectivity ADC3 Channel selection Fast channel ADC3_INP1 Fast channel ADC3_INN1 ADC3_INP2 Fast channel ADC3_INN2 ADC3_INP3 Fast channel ADC3_INN3 ADC3_INP4 Fast channel ADC3_INN4 ADC3_INP5 Fast channel ADC345_INN5 ADC345_INP6 Slow channel ADC345_INN6 REF+ ADC345_INP7 Slow channel ADC345_INN7 ADC345_INP8 Slow channel...
Page 571: Figure 84. Adc4 Connectivity
RM0440 Analog-to-digital converters (ADC) Figure 84. ADC4 connectivity ADC4 Channel selection Fast channel ADC4_INP1 Fast channel ADC4_INN1 ADC4_INP2 Fast channel ADC4_INN2 ADC4_INP3 Fast channel ADC4_INN3 ADC4_INP4 Fast channel ADC4_INN4 ADC4_INP5 Fast channel ADC345_INN5 ADC345_INP6 Slow channel ADC345_INN6 REF+ ADC345_INP7 Slow channel ADC345_INN7 ADC345_INP8 Slow channel...
Page 572: Figure 85. Adc5 Connectivity
Analog-to-digital converters (ADC) RM0440 Figure 85. ADC5 connectivity ADC5 Channel selection Fast channel ADC5_INP1 Fast channel ADC5_INN1 ADC5_INP2 Fast channel OPAMP5 internal Fast channel output Fast channel OPAMP4 internal Fast channel output Reserved ADC345_INP6 Slow channel ADC345_INN6 REF+ ADC345_INP7 Slow channel ADC345_INN7 ADC345_INP8 Slow channel...
Page 573 RM0440 Analog-to-digital converters (ADC) 20.4.5 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors.
Page 574 Analog-to-digital converters (ADC) RM0440 20.4.7 Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by writing into bits DIFSEL[18:1] in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). In single-ended input mode, the analog voltage to be converted for channel “i”...
Page 575: Figure 86. Adc Calibration
RM0440 Analog-to-digital converters (ADC) The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration.
Page 576: Figure 87. Updating The Adc Calibration Factor
Analog-to-digital converters (ADC) RM0440 Figure 87. Updating the ADC calibration factor Converting channel Ready (not converting) Ready Converting channel ADC state (Single ended) (Single ended) Updating calibration Internal calibration factor[6:0] Start conversion (hardware or sofware) WRITE ADC_CALFACT CALFACT_S[6:0] by s/w by h/w MSv30529V2 Converting single-ended and differential analog inputs with a single ADC...
Page 577 RM0440 Analog-to-digital converters (ADC) 20.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 20.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of t before it starts converting accurately, as shown in Figure...
Page 578: Figure 89. Enabling / Disabling The Adc
Analog-to-digital converters (ADC) RM0440 Figure 89. Enabling / Disabling the ADC ADEN STAB ADRDY ADDIS Converting CH Startup state by S/W by H/W MSv30264V2 20.4.10 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0).
Page 579 RM0440 Analog-to-digital converters (ADC) 20.4.11 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC: • 5 fast analog inputs coming from GPIO pads (ADC _INP/INN[1..5]) • Up to 13 slow analog inputs coming from GPIO pads (ADC _INP/INN[6..18]).
Page 580 Analog-to-digital converters (ADC) RM0440 20.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.
Page 581: Figure 90. Bulb Mode Timing Diagram
RM0440 Analog-to-digital converters (ADC) Figure 90. Bulb mode timing diagram Normal (discontinuous) mode ADC state idle sample conversion idle sample conversion idle Trigger BULB (continuous) mode sample conversion sample conversion sample idle ADC state Trigger Sampling time programmed in SMP bits MSv46157V2 Sampling time control trigger mode When the SMPTRIG bit is set, the sampling time programmed though SMPx bits is not...
Page 582 Analog-to-digital converters (ADC) RM0440 20.4.13 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADC_CR register (for a regular channel) •...
Page 583 RM0440 Analog-to-digital converters (ADC) Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously.
Page 584: Figure 91. Analog To Digital Conversion Time
Analog-to-digital converters (ADC) RM0440 20.4.16 ADC timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [2.5 + 12.5 ] x T CONV...
Page 585: Figure 92. Stopping Ongoing Regular Conversions
RM0440 Analog-to-digital converters (ADC) Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 92. Stopping ongoing regular conversions Trigger Trigger Convert Sample Sample ADC state Ch(N-1) Ch(N-1) Ch(N) JADSTART Cleared by Cleared by ADSTART...
Page 586: Table 150. Configuring The Trigger Polarity For Regular External Triggers
Analog-to-digital converters (ADC) RM0440 20.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.
Page 587: Table 152. Adc1/2 - External Triggers For Regular Channels
RM0440 Analog-to-digital converters (ADC) Note: The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 20.4.21: Queue of context for injected conversions on page 594 Each ADC master shares the same input triggers with its ADC slave as described in Figure Figure 94.
Page 588: Table 153. Adc1/2 - External Trigger For Injected Channels
Analog-to-digital converters (ADC) RM0440 Table 152. ADC1/2 - External triggers for regular channels (continued) Name Source Type EXTSEL[4:0] adc_ext_trg9 TIM1_TRGO Internal signal from on-chip timers 01001 adc_ext_trg10 TIM1_TRGO2 Internal signal from on-chip timers 01010 adc_ext_trg11 TIM2_TRGO Internal signal from on-chip timers 01011 adc_ext_trg12 TIM4_TRGO...
Page 589: Table 154. Adc3/4/5 - External Triggers For Regular Channels
RM0440 Analog-to-digital converters (ADC) Table 153. ADC1/2 - External trigger for injected channels (continued) Name Source Type JEXTSEL[4:0] adc_jext_trg9 TIM8_TRGO Internal signal from on-chip timers 01001 adc_jext_trg10 TIM8_TRGO2 Internal signal from on-chip timers 01010 adc_jext_trg11 TIM3_CC3 Internal signal from on-chip timers 01011 adc_jext_trg12 TIM3_TRGO...
Page 590: Table 155. Adc3/4/5 - External Triggers For Injected Channels
Analog-to-digital converters (ADC) RM0440 Table 154. ADC3/4/5 - External triggers for regular channels (continued) Name Source Type EXTSEL[4:0] adc_ext_trg9 TIM1_TRGO Internal signal from on-chip timers 01001 adc_ext_trg10 TIM1_TRGO2 Internal signal from on-chip timers 01010 adc_ext_trg11 TIM2_TRGO Internal signal from on-chip timers 01011 adc_ext_trg12 TIM4_TRGO...
Page 591 RM0440 Analog-to-digital converters (ADC) Table 155. ADC3/4/5 - External triggers for injected channels (continued) Name Source Type JEXTSEL[4:0] adc_jext_trg9 TIM8_TRGO Internal signal from on-chip timers 01001 adc_jext_trg10 TIM8_TRGO2 Internal signal from on-chip timers 01010 adc_jext_trg11 TIM1_CC3 Internal signal from on-chip timers 01011 adc_jext_trg12 TIM3_TRGO...
Page 592 Analog-to-digital converters (ADC) RM0440 reset and the injected channel sequence switches are launched (all the injected channels are converted once). Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.
Page 593: Figure 95. Injected Conversion Latency
RM0440 Analog-to-digital converters (ADC) Figure 95. Injected conversion latency adc_ker_ck Injection event Reset ADC max. latency MSv43771V1 1. The maximum latency value can be found in the electrical characteristics of the STM32G4xx datasheet. 20.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.
Page 594 Analog-to-digital converters (ADC) RM0440 Note: When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup.
Page 595 RM0440 Analog-to-digital converters (ADC) All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: • The JSQR register can be written at any moment even when injected conversions are ongoing.
Page 596: Figure 96. Example Of Jsqr Queue Of Context (Sequence Change)
Analog-to-digital converters (ADC) RM0440 Behavior when changing the trigger or sequence context Figure 96 Figure 97 show the behavior of the context Queue when changing the sequence or the triggers. Figure 96. Example of JSQR queue of context (sequence change) Write JSQR JSQR queue EMPTY...
Page 597: Figure 98. Example Of Jsqr Queue Of Context With Overflow Before Conversion
RM0440 Analog-to-digital converters (ADC) Queue of context: Behavior when a queue overflow occurs Figure 98 Figure 99 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 98. Example of JSQR queue of context with overflow before conversion =>...
Page 598: Figure 100. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=0)
Analog-to-digital converters (ADC) RM0440 It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). •...
Page 599: Figure 101. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=1)
RM0440 Analog-to-digital converters (ADC) Figure 101. Example of JSQR queue of context with empty queue (case JQM=1) Queue becomes empty and triggers are ignored because JQM=1 Write JSQR JSQR EMPTY P1,P2 EMPTY EMPTY queue Ignored Ignored Trigger 1 EMPTY EMPTY (0x0000) EMPTY J context (returned by reading JQSR)
Page 600: Figure 103. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs During An Ongoing Conversion And A New
Analog-to-digital converters (ADC) RM0440 Figure 103. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. Queue is flushed and maintains the last active context (P2 is lost) Write JSQR JSQR EMPTY...
Page 601: Figure 105. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=1)
RM0440 Analog-to-digital converters (ADC) Figure 105. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) Queue is flushed and becomes empty (P2 is lost) Write JSQR EMPTY P1, P2 EMPTY EMPTY JSQR queue Reset by H/W by S/W JADSTP JADSTART Reset by S/W by H/W...
Page 602: Figure 107. Flushing Jsqr Queue Of Context By Setting Addis=1 (Jqm=1)
Analog-to-digital converters (ADC) RM0440 Figure 107. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) Queue is flushed and beomes empty (JSQR is read as 0x0000) JSQR queue P1, P2 EMPTY Reset ADDIS by S/W by H/W ADC J context EMPTY (0x0000) (returned by reading JSQR) ADC state...
Page 603: Table 156. Tsar Timings Depending On Resolution
RM0440 Analog-to-digital converters (ADC) Table 156. T timings depending on resolution (ADC clock cycles) CONV (ns) at (ns) at CONV (with Sampling Time= (bits) = 30 MHz = 30 MHz (ADC clock cycles) 2.5 ADC clock cycles) 12.5 ADC clock cycles 416.67 ns 15 ADC clock cycles 500.0 ns...
Page 604: Figure 108. Single Conversions Of A Sequence, Software Trigger
Analog-to-digital converters (ADC) RM0440 20.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 108. Single conversions of a sequence, software trigger ADSTART CH10 CH17 CH10 CH17 ADC state ADC_DR by s/w by h/w Indicative timings MS30549V1 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 109.
Page 605: Figure 110. Single Conversions Of A Sequence, Hardware Trigger
RM0440 Analog-to-digital converters (ADC) Figure 110. Single conversions of a sequence, hardware trigger ADSTART TRGX ADC state READY ADC_DR Indicative timings by s/w by h/w triggered ignored MS31013V2 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2.
Page 606: Table 157. Offset Computation Versus Data Resolution
Analog-to-digital converters (ADC) RM0440 20.4.26 Data management Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide.
Page 607: Figure 112. Right Alignment (Offset Disabled, Unsigned Value)
RM0440 Analog-to-digital converters (ADC) Table 157. Offset computation versus data resolution (continued) Subtraction between raw converted data and offset Resolution Result Comments (bits converted RES[1:0]) Offset Data, left aligned DATA[11:4],00 Signed The user must configure OFFSET[3:0] 10: 8-bit OFFSET[11:0] 8-bit data to “0000”...
Page 608: Figure 113. Right Alignment (Offset Enabled, Signed Value)
Analog-to-digital converters (ADC) RM0440 Figure 113. Right alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT D11 10-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT 8-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT 6-bit data bit15 bit7...
Page 609: Figure 115. Left Alignment (Offset Enabled, Signed Value)
RM0440 Analog-to-digital converters (ADC) Figure 115. Left alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT D11 10-bit data bit15 bit7 bit0 SEXT D9 8-bit data bit15 bit7 bit0 SEXT D7 6-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT MS31018V1 Gain compensation...
Page 610: Figure 116. Example Of Overrun (Ovr)
Analog-to-digital converters (ADC) RM0440 ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1.
Page 611 RM0440 Analog-to-digital converters (ADC) Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software.
Page 612 Analog-to-digital converters (ADC) RM0440 DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.
Page 613: Figure 117. Autodly=1, Regular Conversion In Continuous Mode, Software Trigger
RM0440 Analog-to-digital converters (ADC) To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure: Wait until JEOS=1 (no more conversions are restarted) Clear JEOS, Set ADSTP=1 Read the regular data. If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set.
Page 614: Figure 118. Autodly=1, Regular Hw Conversions Interrupted By Injected Conversions
Analog-to-digital converters (ADC) RM0440 Figure 118. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) Not ignored Ignored (occurs during injected sequence) Regular trigger ADC state regular regular injected regular regular injected regular DLY (CH1) DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR read access...
Page 615: (Discen=1, Jdiscen=1)
RM0440 Analog-to-digital converters (ADC) Figure 119. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) Not ignored Ignored (occurs during injected sequence) Regular trigger DLY RDYCH2 RDY CH2 RDY CH5 RDY CH1 state regular regular regular regular injected injected regular DLY (CH1) DLY (CH1)
Page 616: Figure 120. Autodly=1, Regular Continuous Conversions Interrupted By Injected Conversions
Analog-to-digital converters (ADC) RM0440 Figure 120. AUTODLY=1, regular continuous conversions interrupted by injected conversions ADSTART state regular regular regular regular injected injected DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR read access ADC_DR Ignored Injected trigger DLY (inj) JEOS ADC_JDR1 ADC_JDR2 by s/w by h/w Indicative timings...
Page 617: Table 158. Analog Watchdog Channel Selection
RM0440 Analog-to-digital converters (ADC) 20.4.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 122. Analog watchdog guarded area Analog voltage Higher threshold Guarded area Lower threshold...
Page 618: Table 159. Analog Watchdog 1 Comparison
Analog-to-digital converters (ADC) RM0440 These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 619: Table 160. Analog Watchdog 2 And 3 Comparison
RM0440 Analog-to-digital converters (ADC) Table 160. Analog watchdog 2 and 3 comparison Analog watchdog comparison between: Resolution Comments Raw converted data, (bits RES[1:0]) Thresholds left aligned 00: 12-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison 01: 10-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison 10: 8-bit...
Page 620: Figure 124. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared By Software)
Analog-to-digital converters (ADC) RM0440 Figure 124. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 STATE inside outside inside outside outside outside inside EOC FLAG not cleared by S/W AWDx FLAG ADCy_AWDx_OUT - Converting regular channels 1,2,3,4,5,6,7 - Regular channels 1,2,3,4,5,6,7 are all guarded MS31026V1 Figure 125.
Page 621 RM0440 Analog-to-digital converters (ADC) Analog watchdog threshold control LTx[11:0] and HTx[11:0] can be changed when an analog-to-digital conversion is ongoing (that is between the start of conversion and the end of conversion of the ADC internal state). If LTx[11:0] and HTx[11:0] are updated during the ADC conversion of the ADC guarded channel, the watchdog function is masked for this conversion.
Page 622: Table 161. Maximum Output Results Versus N And M (Gray Cells Indicate Truncation)
Analog-to-digital converters (ADC) RM0440 Figure 127. 20-bit to 16-bit result truncation Raw 20-bit data Shifting Truncation and rounding MS34453V1 Figure 128 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 128. Numerical example with 5-bit shift and rounding Raw 20-bit data Final result after 5-bit shift and rounding to nearest...
Page 623 RM0440 Analog-to-digital converters (ADC) conversions, with an equivalent delay equal to N x T = N x (t ). The flags are CONV SMPL set as follow: • The end of the sampling phase (EOSMP) is set after each sampling phase •...
Page 624: Figure 129. Triggered Regular Oversampling Mode (Trovs Bit = 1)
Analog-to-digital converters (ADC) RM0440 If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1. Figure 129. Triggered regular oversampling mode (TROVS bit = 1) Trigger Trigger CONT=0 DISCEN = 1 TROVS = 0 Ch(N) Ch(N) Ch(N)
Page 625: Figure 130. Regular Oversampling Modes (4X Ratio)
RM0440 Analog-to-digital converters (ADC) Figure 130. Regular oversampling modes (4x ratio) Oversampling Oversampling stopped continued Regular channels Ch(N) Ch(N) Ch(N) Ch(N) Ch(M) Ch(M) Ch(M) Ch(M) Ch(M) Ch(O) Abort Trigger Injected channels Ch(J) Ch(K) JEOC Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X Oversampling Oversampling aborted...
Page 626: Figure 132. Triggered Regular Oversampling With Injection
Analog-to-digital converters (ADC) RM0440 Triggered regular oversampling with injected conversions It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 132 below.
Page 627: Table 162. Oversampler Operating Modes Summary
RM0440 Analog-to-digital converters (ADC) Combined modes summary Table 162 below summarizes all combinations, including modes not supported. Table 162. Oversampler operating modes summary Oversampler mode Regular Injected Triggered Oversampling Oversampling ROVSM Regular mode Comment ROVSE JOVSE 0 = continued TROVS 1 = resumed Regular continued mode Not supported...
Page 628 Analog-to-digital converters (ADC) RM0440 In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit.
Page 629: Figure 134. Dual Adc Block Diagram (1)
RM0440 Analog-to-digital converters (ADC) Figure 134. Dual ADC block diagram Regular data register (16- bits) Injected data registers (4 Internal analog inputs x16-bits) ADCx_INN1 Regular ADCx_INP1 channels ADCx_INN2 Slave ADC ADCx_INP2 Injected channels Internal triggers Regular data register (16- bits) ADCx_INN16 Injected data registers (4 ADCx_INP16...
Page 630: Figure 135. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0440 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the ADC_JSQR register).
Page 631 RM0440 Analog-to-digital converters (ADC) ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels.
Page 632: Figure 136. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0440 Figure 136. Regular simultaneous mode on 16 channels: dual ADC mode CH16 MASTER ADC SLAVE ADC CH16 CH14 CH13 CH12 Trigger End of regular sequence on MASTER and SLAVE ADC Sampling Conversion ai16054b If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n”...
Page 633: Figure 137. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
RM0440 Analog-to-digital converters (ADC) conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase.
Page 634: Figure 138. Interleaved Mode On 1 Channel In Single Conversion Mode: Dual Adc Mode
Analog-to-digital converters (ADC) RM0440 Figure 138. Interleaved mode on 1 channel in single conversion mode: dual ADC mode 0.5 ADCCLK 0.5 ADCCLK cycle cycle MASTER ADC SLAVE ADC Trigger 4 ADCCLK End of conversion on 4 ADCCLK End of conversion on cycles master and slave ADC cycles...
Page 635: Figure 140. Alternate Trigger: Injected Group Of Each Adc
RM0440 Analog-to-digital converters (ADC) When the 1st trigger occurs, all injected master ADC channels in the group are converted. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted. And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.
Page 636: Figure 141. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Mode
Analog-to-digital converters (ADC) RM0440 If the injected discontinuous mode is enabled for both master and slave ADCs: • When the 1st trigger occurs, the first injected channel of the master ADC is converted. • When the 2nd trigger occurs, the first injected channel of the slave ADC is converted. •...
Page 637: Figure 142. Alternate + Regular Simultaneous
RM0440 Analog-to-digital converters (ADC) Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.
Page 638: Figure 144. Interleaved Single Channel Ch0 With Injected Sequence Ch11, Ch12
Analog-to-digital converters (ADC) RM0440 Figure 144. Interleaved single channel CH0 with injected sequence CH11, CH12 ADC1 (master) Conversions aborted ADC2 (slave) read read read read CH11 CH11 CH12 CH12 Legend: Injected trigger Resume (always restart with the master) Sampling Conversion MS34461V1 Figure 145.
Page 639: Figure 147. Dma Requests In Regular Simultaneous Mode When Mdma=0B00
RM0440 Analog-to-digital converters (ADC) DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 147: DMA Requests in regular simultaneous mode when MDMA=0b00).
Page 640: Figure 148. Dma Requests In Regular Simultaneous Mode When Mdma=0B10
Analog-to-digital converters (ADC) RM0440 Figure 148. DMA requests in regular simultaneous mode when MDMA=0b10 Trigger Trigger Trigger Trigger ADC Master regular ADC Slave EOC ADC Slave regular ADC Slave EOC DMA request from ADC Master DMA request from ADC Slave Configuration where each sequence contains only one conversion MSv31033V2 Figure 149.
Page 641 RM0440 Analog-to-digital converters (ADC) Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. •...
Page 642: Figure 150. Temperature Sensor Channel Block Diagram
To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area.
Page 643: Figure 151. Vbat Channel Block Diagram
RM0440 Analog-to-digital converters (ADC) Where: • TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP. • TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP. • TS_DATA is the actual temperature sensor output value converted by ADC. Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.
Page 644: Figure 152. Vrefint Channel Block Diagram
Analog-to-digital converters (ADC) RM0440 20.4.33 Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (V ) to have a reference point for REFINT evaluating the ADC V voltage level. REF+ The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_INP0).
Page 645: Table 163. Adc Interrupts Per Each Adc
RM0440 Analog-to-digital converters (ADC) By replacing V by the formula provided above, the absolute voltage value is given by REF+ the following formula × × 3.0 V VREFINT_CAL ADC_DATA ---------------------------------------------------------------------------------------------------- - CHANNELx × VREFINT_DATA FULL_SCALE For applications where V is known and ADC converted values are right-aligned, the absolute voltage value can be obtained by using the following formula: ------------------------------------ - ×...
Page 646 Analog-to-digital converters (ADC) RM0440 Table 163. ADC interrupts per each ADC (continued) Interrupt event Event flag Enable control bit Analog watchdog 1 status bit is set AWD1 AWD1IE Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE End of sampling phase...
Page 647 RM0440 Analog-to-digital converters (ADC) 20.6 ADC registers (for each ADC) Refer to Section 1.2 on page 110 for a list of abbreviations used in register descriptions. 20.6.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 648 Analog-to-digital converters (ADC) RM0440 Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
Page 649 RM0440 Analog-to-digital converters (ADC) 20.6.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JQOVF AWD3I AWD2I AWD1I EOSMP ADRDY Res. Res.
Page 650 Analog-to-digital converters (ADC) RM0440 Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing).
Page 651 RM0440 Analog-to-digital converters (ADC) 20.6.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x2000 0000 ADCA ADCA DEEP ADVREG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF JADST JADST ADSTA Res. Res. Res. Res. Res.
Page 652 Analog-to-digital converters (ADC) RM0440 Bits 27:6 Reserved, must be kept at reset value. Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 653 RM0440 Analog-to-digital converters (ADC) Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: –...
Page 654 Analog-to-digital converters (ADC) RM0440 20.6.4 ADC configuration register (ADC_CFGR) Address offset: 0x0C Reset value: 0x8000 0000 JAWD1 AWD1 AWD1S JDISC DISC JQDIS AWD1CH[4:0] JAUTO DISCNUM[2:0] EXTSE EXTSE EXTSE EXTSE EXTSE ALIGN CONT EXTEN[1:0] RES[1:0] Res. Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : 0: Injected Queue enabled 1: Injected Queue disabled...
Page 655 RM0440 Analog-to-digital converters (ADC) Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on regular channels 1: Analog watchdog 1 enabled on regular channels Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 656 Analog-to-digital converters (ADC) RM0440 Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.
Page 657 RM0440 Analog-to-digital converters (ADC) Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges...
Page 658 Analog-to-digital converters (ADC) RM0440 Bit 2 Reserved, must be kept at reset value. Bit 1 DMACFG: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. 0: DMA One Shot mode selected 1: DMA Circular mode selected For more details, refer to...
Page 659 RM0440 Analog-to-digital converters (ADC) Bits 31:28 Reserved, must be kept at reset value. Bit 27 SMPTRIG: Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. 0: Sampling time control trigger mode disabled 1: Sampling time control trigger mode enabled The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge.
Page 660 Analog-to-digital converters (ADC) RM0440 Bit 9 TROVS: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling 0: All oversampled conversions for a channel are done consecutively following a trigger 1: Each oversampled conversion for a channel needs a new trigger Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 661 RM0440 Analog-to-digital converters (ADC) 20.6.6 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x14 Reset value: 0x0000 0000 SMPPL Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 SMPPLUS: Addition of one clock cycle to the sampling time 1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers.
Page 662 Analog-to-digital converters (ADC) RM0440 Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. 000: 2.5 ADC clock cycles 001: 6.5 ADC clock cycles 010: 12.5 ADC clock cycles...
Page 663 RM0440 Analog-to-digital converters (ADC) Bits 15: Reserved, must be kept at reset value. Bits 14:12 AWDFILT: Analog watchdog filtering parameter This bit is set and cleared by software. 000: No filtering 001: two consecutive detection generates an AWDx flag or an interrupt 111: Eight consecutive detection generates an AWDx flag or an interrupt Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 664 Analog-to-digital converters (ADC) RM0440 20.6.10 ADC watchdog threshold register 3 (ADC_TR3) Address offset: 0x28 Reset value: 0x00FF 0000 Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0] Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3.
Page 665 RM0440 Analog-to-digital converters (ADC) Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 666 Analog-to-digital converters (ADC) RM0440 Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 667 RM0440 Analog-to-digital converters (ADC) Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 668 Analog-to-digital converters (ADC) RM0440 Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 669 RM0440 Analog-to-digital converters (ADC) Bits 31:27 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the injected conversion sequence.c Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).
Page 670 Analog-to-digital converters (ADC) RM0440 Bits 8:7 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled 00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge...
Page 671 RM0440 Analog-to-digital converters (ADC) Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 672 Analog-to-digital converters (ADC) RM0440 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 20.4.26: Data management.
Page 673 RM0440 Analog-to-digital converters (ADC) Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD3CH[18:0]: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled...
Page 674 Analog-to-digital converters (ADC) RM0440 Bits 31:23 Reserved, must be kept at reset value. Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors.
Page 675 RM0440 Analog-to-digital converters (ADC) 20.7 ADC common registers These registers define the control and status registers common to master and slave ADCs: 20.7.1 ADC x common status register (ADCx_CSR) (x=1/2 or 3/4/5) Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs.
Page 676 Analog-to-digital converters (ADC) RM0440 Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. Bits 15:11 Reserved, must be kept at reset value. Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Page 677 RM0440 Analog-to-digital converters (ADC) Bits 31:25 Reserved, must be kept at reset value. Bit 24 VBATSEL: VBAT selection This bit is set and cleared by software to control VBAT. 0: V channel disabled. 1: V channel enabled Bit 23 VSENSESEL: V selection This bit is set and cleared by software to control V 0: Temperature sensor channel disabled...
Page 678: Table 164. Delay Bits Versus Adc Resolution
Analog-to-digital converters (ADC) RM0440 Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. 00: MDMA mode disabled 01: Reserved 10: MDMA mode enabled for 12 and 10-bit resolution 11: MDMA mode enabled for 8 and 6-bit resolution Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 679 RM0440 Analog-to-digital converters (ADC) Table 164. DELAY bits versus ADC resolution (continued) DELAY bits 12-bit resolution 10-bit resolution 8-bit resolution 6-bit resolution 0011 4 * T 4 * T 4 * T 4 * T adc_ker_ck adc_ker_ck adc_ker_ck adc_ker_ck 0100 5 * T 5 * T 5 * T...
Page 680: Table 165. Adc Global Register Map
Analog-to-digital converters (ADC) RM0440 20.7.3 ADC x Common regular data register for dual mode (ADCx_CDR) (x=1/2 or 3/4/5) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and ADC5.
Page 681: Table 166. Adc Register Map And Reset Values For Each Adc
RM0440 Analog-to-digital converters (ADC) Table 166. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) Offset Register ADC_ISR 0x00 Reset value ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value DISCNUM AWD1CH[4:0] ADC_CFGR [2:0] [1:0] 0x0C...
Page 682 Analog-to-digital converters (ADC) RM0440 Table 166. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register 0x44- Reserved Res. 0x48 JEXTSEL JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0] ADC_JSQR [4:0] 0x4C Reset value 0x50- Reserved Res.
Page 683: Common Registers) Offset = 0X300
RM0440 Analog-to-digital converters (ADC) Table 166. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register DIFSEL[18:0] ADC_DIFSEL 0xB0 Reset value CALFACT_D[6:0] CALFACT_S[6:0] ADC_CALFACT 0xB4 Reset value GCOMP[13:0] ADC_GCOMP 0xC0 Reset value Table 167.
Page 684 Digital-to-analog converter (DAC) RM0440 Digital-to-analog converter (DAC) 21.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 685: Table 168. Dac Implementation
RM0440 Digital-to-analog converter (DAC) 21.3 DAC implementation Table 168. DAC implementation DAC features DAC1 DAC2 DAC3 DAC4 Dual channel Output buffer DAC1_OUT1 on PA4 I/O connection DAC2_OUT1 on PA6 No connection to a GPIO DAC1_OUT2 on PA5 Maximum sampling 1MSPS 15MSPS time RM0440 Rev 1...
Page 686: Figure 153. Dual-Channel Dac Block Diagram
Digital-to-analog converter (DAC) RM0440 21.4 DAC functional description 21.4.1 DAC block diagram Figure 153. Dual-channel DAC block diagram VDDA Offset calibration dac_ch1_trg0 OTRIM1[5:0] bits TRIG MODE1 bits dac_ch1_trg15 Buffer TSEL1 DOR1 [3:0] converter 1 bits 12-bit dac_ch1_dma Sample & Hold registers Control registers TSAMPLE1...
Page 687: Table 169. Dac Input/Output Pins
RM0440 Digital-to-analog converter (DAC) 21.4.2 DAC pins and internal signals The DAC includes: • Up to two output channels • The DAC_OUTx can be disconnected from the output pin and used as an ordinary GPIO • The dac_outx can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).
Page 688: Figure 154. Data Registers In Single Dac Channel Mode
Digital-to-analog converter (DAC) RM0440 21.4.3 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a t startup time. WAKEUP DACxRDY bit is set in the DAC_SR register when the DAC interface is ready to accept data. Writing new data or asserting the trigger is not allowed when ENx bit is set while DACxRDY signal is reset.
Page 689: Table 171. Data Format (Case Of 12-Bit Data)
RM0440 Digital-to-analog converter (DAC) Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory- mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.
Page 690: Table 172. Hfsel Description
Digital-to-analog converter (DAC) RM0440 21.4.5 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one dac_hclk clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset).
Page 691: Table 173. Dac1 Channel Trigger And Sawtooth Reset Trigger Selection
RM0440 Digital-to-analog converter (DAC) 21.4.6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation: ------------- - ×...
Page 692: Table 174. Dac1 Sawtooth Increment Trigger Selection
Digital-to-analog converter (DAC) RM0440 Table 173. DAC1 channel trigger and sawtooth reset trigger selection (continued) TSELx[3:0], Source Type STRSTTRIGSELx[3:0] Internal signal from on-chip TIM3_TRGO 1000 timers Internal signal from on-chip hrtim_dac_reset_trg1 1001 timers Internal signal from on-chip hrtim_dac_reset_trg2 1010 timers Internal signal from on-chip hrtim_dac_reset_trg3 1011...
Page 693: Table 175. Dac2 Channel Trigger And Sawtooth Reset Trigger Selection
RM0440 Digital-to-analog converter (DAC) Table 175. DAC2 channel trigger and sawtooth reset trigger selection TSELx[3:0], Source Type STRSTTRIGSELx[3:0] SWTRIG Software control bit 0000 Internal signal from on-chip TIM8_TRGO 0001 timers Internal signal from on-chip TIM7_TRGO 0010 timers Internal signal from on-chip TIM15_TRGO 0011 timers...
Page 694: Table 177. Dac3 Channel Trigger And Sawtooth Reset Trigger Selection
Digital-to-analog converter (DAC) RM0440 Table 176. DAC2 sawtooth increment trigger selection (continued) Source Type STINCTRIGSELx[3:0] Internal signal from on-chip TIM2_TRGO 0100 timers Internal signal from on-chip TIM4_TRGO 0101 timers EXTI10 External pin 0110 Internal signal from on-chip TIM6_TRGO 0111 timers Internal signal from on-chip TIM3_TRGO 1000...
Page 695: Table 178. Dac3 Sawtooth Increment Trigger Selection
RM0440 Digital-to-analog converter (DAC) Table 177. DAC3 channel trigger and sawtooth reset trigger selection (continued) TSELx[3:0], Source Type STRSTTRIGSELx[3:0] Internal signal from on-chip TIM3_TRGO 1000 timers Internal signal from on-chip hrtim_dac_reset_trg1 1001 timers Internal signal from on-chip hrtim_dac_reset_trg2 1010 timers Internal signal from on-chip hrtim_dac_reset_trg3 1011...
Page 696: Table 179. Dac4 Channel Trigger And Sawtooth Reset Trigger Selection
Digital-to-analog converter (DAC) RM0440 Table 178. DAC3 sawtooth increment trigger selection (continued) Source Type STINCTRIGSELx[3:0] Internal signal from on-chip hrtim_dac_step_trg3 1011 timers Internal signal from on-chip hrtim_dac_step_trg4 1100 timers Internal signal from on-chip hrtim_dac_step_trg5 1101 timers Internal signal from on-chip hrtim_dac_step_trg6 1110 timers...
Page 697: Table 180. Dac4 Sawtooth Increment Trigger Selection
RM0440 Digital-to-analog converter (DAC) Table 179. DAC4 channel trigger and sawtooth reset trigger selection (continued) TSELx[3:0], Source Type STRSTTRIGSELx[3:0] Internal signal from on-chip hrtim_dac_reset_trg6 1110 timers Internal signal from on-chip hrtim_dac_trg1 1111 timers Table 180. DAC4 sawtooth increment trigger selection Source Type STINCTRIGSELx[3:0]...
Page 698 Digital-to-analog converter (DAC) RM0440 21.4.8 DMA requests Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the value of the DAC_DHRx register is transferred into the DAC_DORx register when the transfer is complete, and a DMA request is generated.
Page 699: Figure 157. Dac Lfsr Register Calculation Algorithm
RM0440 Digital-to-analog converter (DAC) The following conditions must be met to change from Double data to single data mode or vice versa: • The DAC must be disabled. • DMAEN bit must be cleared (ENx=0 and DMAENx=0). 21.4.9 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available.
Page 700: Figure 159. Dac Triangle Wave Generation
Digital-to-analog converter (DAC) RM0440 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. 21.4.10 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”.
Page 701: Figure 161. Dac Sawtooth Wave Generation (Stdirx=0)
RM0440 Digital-to-analog converter (DAC) 21.4.11 Sawtooth wave generation The DAC can generate a sawtooth waveform. Specific register settings for the initial value, increment value and direction control are required: • DAC sawtooth wave generation is selected by setting WAVEx[1:0] to 11 in the DAC_CR register.
Page 702: Figure 163. Dac Sawtooth Stinctrig And Strsttrig Priority (Stdir = 0)
Digital-to-analog converter (DAC) RM0440 The STRSTTRIG signal has higher priority than STINCTRIG. The trigger signal cannot be faster than the DAC_DORx update rate defined in the Table 172: HFSEL description. If STINCTRIG is asserted faster than the allowed data update rate, the STINCTRIG trigger is ignored.
Page 703: Table 181. Sample And Refresh Timings
RM0440 Digital-to-analog converter (DAC) Sample and Hold mode In sample and Hold mode, the DAC core converts data on a triggered conversion, and then holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption.
Page 704: Figure 164. Dac Sample And Hold Mode Phase Diagram
Digital-to-analog converter (DAC) RM0440 Example of the sample and refresh time calculation with output buffer on The values used in the example below are provided as indication only. Please refer to the product datasheet for product data. = 100 nF = 3.0 V Sampling phase: = 7 μs + (10 * 2000 * 100 * 10...
Page 705: Table 182. Channel Output Modes Summary
RM0440 Digital-to-analog converter (DAC) To disabled the output buffer, The MODEx[2:0] bits in DAC_MCR register should be: • 110: DAC is connected to external pin and to on chip peripherals • 111: DAC is connected to on chip peripherals When MODEx[2:0] bits in DAC_MCR register is equal to 111. An internal capacitor, C will Lint hold the voltage output of the DAC Core and then drive it to on-chip peripherals.
Page 706 Digital-to-analog converter (DAC) RM0440 Two calibration techniques are provided: • Factory trimming (always enabled) The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in DAC_CCR register is the factory trimming value and it is loaded once DAC digital interface is reset.
Page 707 RM0440 Digital-to-analog converter (DAC) 21.4.14 Dual DAC channel conversion modes (if available) To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.
Page 708 Digital-to-analog converter (DAC) RM0440 Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.
Page 709 RM0440 Digital-to-analog converter (DAC) transferred into DAC_DOR1 (three dac_hclk clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later).
Page 710 Digital-to-analog converter (DAC) RM0440 When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three dac_hclk clock cycles). Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2.
Page 711 RM0440 Digital-to-analog converter (DAC) At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2...
Page 712: Table 183. Effect Of Low-Power Modes On Dac
Digital-to-analog converter (DAC) RM0440 21.5 DAC low-power modes Table 183. Effect of low-power modes on DAC Mode Description Sleep No effect, DAC used with DMA Low-power run No effect. Low-power sleep No effect. DAC used with DMA. DAC remains active with a static value, if Sample and Hold mode is Stop 0 / Stop 1 selected using LSI/LSE clock Standby...
Page 713 RM0440 Digital-to-analog converter (DAC) 21.7 DAC registers Refer to Section 1 on page 71 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 21.7.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU DMAE...
Page 714 Digital-to-analog converter (DAC) RM0440 Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 715 RM0440 Digital-to-analog converter (DAC) Bit 14 CEN1: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channelis disabled) Otherwise, the write operation is ignored.
Page 716 Digital-to-analog converter (DAC) RM0440 Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 Refer to the trigger selection tables for the details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bit 1 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger.
Page 717 RM0440 Digital-to-analog converter (DAC) Bit 15:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one dac_hclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.
Page 718 Digital-to-analog converter (DAC) RM0440 21.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 DACC1DHRB[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Res. Bits 31:20 DACC1DHRB[11:0]: DAC channel1 12-bit left-aligned data B These bits are written by software.
Page 719 RM0440 Digital-to-analog converter (DAC) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. DACC2DHRB[11:0] Res. Res. Res. Res. DACC2DHR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHRB[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2 when the DAC operates in DMA Double data mode.
Page 720 Digital-to-analog converter (DAC) RM0440 Address offset: 0x1C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHRB[7:0] DACC2DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHRB[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software.
Page 721 RM0440 Digital-to-analog converter (DAC) 21.7.10 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 DACC2DHR[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Res. Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 19:16 Reserved, must be kept at reset value.
Page 722 Digital-to-analog converter (DAC) RM0440 21.7.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. DACC1DORB[11:0] Res. Res. Res. Res. DACC1DOR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC1DORB[11:0]: DAC channel1 data output These bits are read-only.
Page 723 RM0440 Digital-to-analog converter (DAC) 21.7.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 CAL_ DMAU DORST DAC2R BWST2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLAG2 rc_w1 CAL_ DMAU DORST DAC1R BWST1 Res. Res.
Page 724 Digital-to-analog converter (DAC) RM0440 Bits 26:16 Reserved, must be kept at reset value. Bit 15 BWST1: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete.
Page 725 RM0440 Digital-to-analog converter (DAC) 21.7.16 DAC mode control register (DAC_MCR) Address offset: 0x3C Reset value: 0x0000 0000 DMAD SINFO Res. Res. Res. Res. Res. Res. OUBLE Res. Res. Res. Res. Res. MODE2[2:0] RMAT2 DMAD HFSEL HFSEL SINFO Res. Res. Res. Res.
Page 726 Digital-to-analog converter (DAC) RM0440 Bits 15:14 HFSEL[1:0]: High frequency interface mode selection 00: High frequency interface mode disabled 01: High frequency interface mode compatible to AHB>80 MHz enabled 10: High frequency interface mode compatible to AHB>160 MHz enabled 11: Reserved Bits 15:14 Reserved, must be kept at reset value.
Page 727 RM0440 Digital-to-analog converter (DAC) Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE1[9:0]: DAC channel1 sample time (only valid in Sample and Hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored.
Page 728 Digital-to-analog converter (DAC) RM0440 Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and Hold mode). Hold time= (THOLD[9:0]) x LSI/LSE clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs.
Page 729 RM0440 Digital-to-analog converter (DAC) 21.7.21 DAC channel1 sawtooth register (DAC_STR1) Address offset: 0x58 Reset value: 0x0000 0000 STINCDATA1[15:0] STDIR Res. Res. Res. STRSTDATA1[11:0] Bits 31:16 STINCDATA1[15:0]: DAC channel1 sawtooth increment value (12.4 bit format) Bits 15:13 Reserved, must be kept at reset value. Bit 12 STDIR1: DAC channel1 sawtooth direction setting This bit is written by software to select the direction of Sawtooth step direction 0: Decrement...
Page 730 Digital-to-analog converter (DAC) RM0440 21.7.23 DAC sawtooth mode register (DAC_STMODR) Address offset: 0x60 Reset value: 0x0000 0000 Res. Res. Res. Res. STINCTRIGSEL2[3:0] Res. Res. Res. Res. STRSTTRIGSEL2[3:0] Res. Res. Res. Res. STINCTRIGSEL1[3:0] Res. Res. Res. Res. STRSTTRIGSEL1[3:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 STINCTRIGSEL2[3:0]: DAC channel2 sawtooth increment trigger selection Refer to the trigger selection tables for the details on trigger configuration and mapping.
Page 731: Table 185. Dac Register Map And Reset Values
RM0440 Digital-to-analog converter (DAC) 21.7.24 DAC register map Table 185 summarizes the DAC registers. Table 185. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHRB[11:0] DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHRB[11:0] DACC1DHR[11:0]...
Page 732 Digital-to-analog converter (DAC) RM0440 Table 185. DAC register map and reset values (continued) Register Offset name DAC_SR 0x34 Reset value DAC_CCR OTRIM2[4:0] OTRIM1[4:0] 0x38 Reset value X X X X MODE2 MODE1 DAC_MCR [2:0] [2:0] 0x3C Reset value DAC_ TSAMPLE1[9:0] SHSR1 0x40 Reset value...
Page 733: Table 186. Vref Buffer Modes
Voltage reference buffer (VREFBUF) Voltage reference buffer (VREFBUF) 22.1 Introduction The STM32G4 Series devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. 22.2...
Page 734 Voltage reference buffer (VREFBUF) RM0440 22.3 VREFBUF registers 22.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 735: Table 187. Vrefbuf Register Map And Reset Values
RM0440 Voltage reference buffer (VREFBUF) 22.3.2 VREFBUF calibration control register (VREFBUF_CCR) Address offset: 0x04 Reset value: 0x0000 00XX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 736: Figure 165. Comparator Block Diagram
Comparator (COMP) RM0440 Comparator (COMP) 23.1 COMP introduction The device embeds up to seven ultra-fast analog comparators. The comparators can be used for a variety of functions including: • Wake-up from low-power mode triggered by an analog signal, • Analog signal conditioning, •...
Page 737: Table 188. Compx Non-Inverting Input Assignment
RM0440 Comparator (COMP) 23.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers. The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The output can also be internally redirected to a variety of timer input for the following purposes: •...
Page 738: Figure 166. Comparator Hysteresis
Comparator (COMP) RM0440 23.3.4 COMP LOCK mechanism The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption.
Page 739: Table 190. Blanking Sources
RM0440 Comparator (COMP) Figure 167. Comparator output blanking Current limit Current Raw comp output Blanking window Final comp output Comp out Comp out (to TIM_BK …) Blank MS30964V1 Table 190. Blanking sources BLANKSEL COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 [2:0] TIM1_OC5 TIM1_OC5...
Page 740 Comparator (COMP) RM0440 Table 191. Comparator behavior in low-power modes (continued) Mode Description Low-power sleep No effect. COMP interrupts cause the device to exit the Low-power sleep mode. No effect on the comparators. Stop Comparator interrupts cause the device to exit the Stop mode. Standby, The COMP registers are powered down and must be reinitialized after exiting Shutdown...
Page 741 RM0440 Comparator (COMP) Bit 31 LOCK: COMP_CxCSR register lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator x control register COMP_CxCSR[31:0]. When locked, all control bits and flags can be read only but not written.
Page 742: Table 192. Comp Register Map And Reset Values
Comparator (COMP) RM0440 Bits 7:4 INMSEL[3:0]: Comparator x signal select for inverting input This bitfield controlled by software selects the signal for the inverting input COMPx_INM of the comparator x, as shown in Table 189: COMPx inverting input assignment. Bits 3:1 Reserved, must be kept at reset value Bit 0 EN: Comparator x enable This bit controlled by software enables the operation of comparator x: 0: Disable...
Page 743 RM0440 Comparator (COMP) Table 192. COMP register map and reset values (continued) Offset Register COMP_C6CSR 0x14 Reset value COMP_C7CSR 0x18 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. RM0440 Rev 1 743/2083...
Page 744 Operational amplifiers (OPAMP) RM0440 Operational amplifiers (OPAMP) 24.1 Introduction The devices embed six operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 64 or with inverting gain ranging from -1 to -63.
Page 745: Table 193. Operational Amplifier Possible Connection
RM0440 Operational amplifiers (OPAMP) The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers configurations should be changed before enabling the OPAEN bit in order to avoid spurious effects on the output. When the output of the operational amplifier is no more needed the operational amplifier can be disabled to save power.
Page 746 Operational amplifiers (OPAMP) RM0440 Table 193. Operational amplifier possible connection (continued) Signal Internal Comment The pin is connected when the OPAMP is ADC2_IN3 OPAMP2_VOUT enabled and OPAMP internal output is ADC2_IN16 disabled. The ADC input is controlled by ADC PB2 (VINM0) OPAMP3_VINM OPAMP3_VOUT or PGA controlled by bits PGA_GAIN and VM_SEL...
Page 747: Figure 168. Standalone Mode: External Gain Setting Mode
RM0440 Operational amplifiers (OPAMP) 24.3.5 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Note: The impedance of the signal must be maintained below a level which avoids the input leakage to create significant artifacts (due to a resistive drop in the source).
Page 748: Figure 169. Follower Configuration
Operational amplifiers (OPAMP) RM0440 Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. • configure VM_SEL bits as “opamp_out connected to OPAMPx_VINM input”, 11 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”, 00 •...
Page 749: Figure 170. Pga Mode, Internal Gain Setting (X2/X4/X8/X16/X32/X64)
RM0440 Operational amplifiers (OPAMP) Programmable gain amplifier mode The procedure to use the OPAMP as programmable gain amplifier is presented hereafter. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, • configure PGA_GAIN bits as “internal Gain 2, 4, 8, 16,32, or 64”, 00000 to 00101 •...
Page 750: Figure 171. Pga Mode, Internal Gain Setting (X2/X4/X8/X16/X32/X64)
Operational amplifiers (OPAMP) RM0440 Programmable gain amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, •...
Page 751: Figure 172. Pga Mode, Non-Inverting Gain Setting (X2/X4/X8/X16/X32/X64)
RM0440 Operational amplifiers (OPAMP) Programmable gain amplifier, non-inverting with external bias or inverting mode The procedure to use the OPAMP to amplify the amplitude of an input signal with bias voltage for non-inverting mode or inverting mode. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, •...
Page 752: Figure 173. Pga Mode, Non-Inverting Gain Setting (X2/X4/X8/X16/X32/X64) Or Inverting Gain Setting (X-1/X-3/X-7/X-15/X-31/X-63) With Filtering
Operational amplifiers (OPAMP) RM0440 Figure 173. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64) or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) with filtering STM32 VINP0 VINP1 VINP2 opamp_out VINP4 or DACx_CHy VINM1 VINM0 Allows optional low-pass filtering Equivalent to VOUT 1. opamp_out can be redirected internally to an ADC channel by setting OPAINTOEN bit. In this case, the I/O on which is mapped the OPAMPx_VOUT is free and can be used for another purpose.
Page 753: Table 194. Operating Modes And Calibration
RM0440 Operational amplifiers (OPAMP) 24.3.7 Calibration The OPAMP offset value is minimized using a trimming circuitry. At startup, the trimming values are initialized with the preset ‘factory’ trimming value. Each operational amplifier can also be trimmed by the user if the opamp is used in conditions different from the factory trimming conditions.
Page 754 Operational amplifiers (OPAMP) RM0440 Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: Set the OPAEN bit in OPAMPx_CSR to 1 to enable the operational amplifier. Set the USERTRIM bit in the OPAMPx_CSR register to 1. Choose a calibration mode (refer to Table 194: Operating modes and calibration).
Page 755: Table 195. Effect Of Low-Power Modes On The Opamp
RM0440 Operational amplifiers (OPAMP) Figure 175. Timer controlled Multiplexer mode CCR6 T1 counter T8 counter ADC sampling points T1 output (1 out of 3) T8 output (1 out of 3) T1 CC6 output arriving on OPAMP input mux OPAMP input selection: Def = default OPAMP input selection Sec = secondary OPAMP input selection MS192230V3...
Page 756 Operational amplifiers (OPAMP) RM0440 24.5 OPAMP registers 24.5.1 OPAMP1 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x00 Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP1_CSR lock This bit is write-once.
Page 757 RM0440 Operational amplifiers (OPAMP) Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 758 Operational amplifiers (OPAMP) RM0440 Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 759 RM0440 Operational amplifiers (OPAMP) 24.5.2 OPAMP2 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x04 Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP2_CSR lock This bit is write-once.
Page 760 Operational amplifiers (OPAMP) RM0440 Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 761 RM0440 Operational amplifiers (OPAMP) Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 762 Operational amplifiers (OPAMP) RM0440 24.5.3 OPAMP3 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x08 Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP3_CSR lock This bit is write-once.
Page 763 RM0440 Operational amplifiers (OPAMP) Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 764 Operational amplifiers (OPAMP) RM0440 Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 765 RM0440 Operational amplifiers (OPAMP) 24.5.4 OPAMP4 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x0C Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP4_CSR lock This bit is write-once.
Page 766 Operational amplifiers (OPAMP) RM0440 Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 767 RM0440 Operational amplifiers (OPAMP) Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 768 Operational amplifiers (OPAMP) RM0440 24.5.5 OPAMP5 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x10 Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP5_CSR lock This bit is write-once.
Page 769 RM0440 Operational amplifiers (OPAMP) Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 770 Operational amplifiers (OPAMP) RM0440 Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 771 RM0440 Operational amplifiers (OPAMP) 24.5.6 OPAMP6 control/status register (OPAMPx_CSR) (x = 1...6) Address offset: 0x14 Reset value: 0x0000 0000 LOCK Res. TRIMOFFSETN TRIMOFFSETP PGA_GAIN USER FORCE PGA_GAIN CALSEL CALON Res. Res. VM_SEL VP_SEL OPAEN INTOEN TRIM. Bit 31 LOCK: OPAMP6_CSR lock This bit is write-once.
Page 772 Operational amplifiers (OPAMP) RM0440 Bits 18:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00000: Non inverting internal gain =2 00001: Non inverting internal gain =4 00010: Non inverting internal gain =8 00011: Non inverting internal gain =16 00100: Non inverting internal gain =32 00101: Non inverting internal gain =64 00110: Not used 00111: Not used...
Page 773 RM0440 Operational amplifiers (OPAMP) Bit 8 OPAINTOEN: Operational amplifier internal output enable. 0: The OPAMP output is connected to the output pin 1: The OPAMP output is connected internally to an ADC channel and disconnected from the output pin Bit 7 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration.
Page 774 Operational amplifiers (OPAMP) RM0440 24.5.7 OPAMP1 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x18 Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP1_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP1_TCMR register as read-only.
Page 775 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 776 Operational amplifiers (OPAMP) RM0440 24.5.8 OPAMP2 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x1C Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP2_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP2_TCMR register as read-only.
Page 777 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 778 Operational amplifiers (OPAMP) RM0440 24.5.9 OPAMP3 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x20 Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP3_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP3_TCMR register as read-only.
Page 779 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 780 Operational amplifiers (OPAMP) RM0440 24.5.10 OPAMP4 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x24 Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP4_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP4_TCMR register as read-only.
Page 781 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 782 Operational amplifiers (OPAMP) RM0440 24.5.11 OPAMP5 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x28 Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP5_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP5_TCMR register as read-only.
Page 783 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 784 Operational amplifiers (OPAMP) RM0440 24.5.12 OPAMP6 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) Address offset: 0x2C Reset value: 0x0000 0000 LOCK Res. T20CM T8CM_ T1CM_ VMS_ Res. VPS_SEL Bit 31 LOCK: OPAMP6_TCMR lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP6_TCMR register as read-only.
Page 785 RM0440 Operational amplifiers (OPAMP) Bit 3 T1CM_EN: TIM1 controlled mux mode enable This bit is set and cleared by software. It is used to control automatically the switch between the default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and VMS_SEL) of the inverting and non inverting inputs.
Page 786: Table 196. Opamp Register Map And Reset Values
Operational amplifiers (OPAMP) RM0440 24.5.13 OPAMP register map Table 196. OPAMP register map and reset values Register Offset name OPAMP1_CSR TRIMOFFSETN TRIMOFFSETP PGA_GAIN 0x00 Reset value OPAMP2_CSR TRIMOFFSETN TRIMOFFSETP PGA_GAIN 0x04 Reset value OPAMP3_CSR TRIMOFFSETN TRIMOFFSETP PGA_GAIN 0x08 Reset value OPAMP4_CSR TRIMOFFSETN TRIMOFFSETP...
Page 787 RM0440 Operational amplifiers (OPAMP) Table 196. OPAMP register map and reset values (continued) Register Offset name OPAMP5_ TCMR 0x28 Reset value OPAMP6_ TCMR 0x2C Reset value Refer to Section 2.2 on page 78 for the register boundary addresses. RM0440 Rev 1 787/2083...
Page 788 True random number generator (RNG) RM0440 True random number generator (RNG) 25.1 Introduction The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.
Page 789: Table 197. Rng Internal Input/Output Signals
RM0440 True random number generator (RNG) 25.3 RNG functional description 25.3.1 RNG block diagram Figure 176 shows the RNG block diagram. Figure 176. RNG block diagram True RNG rng_it Conditioning logic Banked Registers RNG_CR control RNG_DR data interface RNG_SR status 128-bit Fault detection AHB clock domain...
Page 790: Figure 177. Entropy Source Model
True random number generator (RNG) RM0440 25.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. The RNG implements the entropy source model pictured Figure 177, and provides three main functions to the application: •...
Page 791 RM0440 True random number generator (RNG) This noise source sampling is independent to the AHB interface clock frequency (rng_hclk). Note: Section 25.6: RNG entropy source validation recommended RNG clock frequencies are given. Post processing The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level.
Page 792 True random number generator (RNG) RM0440 Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features to the value recommended for register: RNG_HCTR (in Section 25.6.2).
Page 793: Figure 178. Rng Initialization Overview
RM0440 True random number generator (RNG) The associated initialization time can be found in Section 25.5: RNG processing time. Figure 178. RNG initialization overview Noise source enable RNGEN=0, then RNGEN=1 Conditioning hardware init Drop samples then check again Error state Generate samples Continuous test(s) not OK...
Page 794 True random number generator (RNG) RM0440 To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 795 RM0440 True random number generator (RNG) Note: The clock error has no impact on generated random numbers, i.e. application can still read RNG_DR register. CEIS is set only when CECS is set to “1” by RNG. Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1”...
Page 796: Table 198. Rng Interrupt Requests
True random number generator (RNG) RM0440 Table 198. RNG interrupt requests Interrupt acronym Interrupt event Event flag Enable control bit Interrupt clear method Data ready flag DRDY None (automatic) Write 0 to SEIS or write Seed error flag SEIS CONDRST to 1 then to 0 Clock error flag CEIS Write 0 to CEIS...
Page 797 RM0440 True random number generator (RNG) 25.7 RNG registers The RNG is associated with a control register, a data register and a status register. 25.7.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 798 True random number generator (RNG) RM0440 25.7.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 799 RM0440 True random number generator (RNG) 25.7.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty.
Page 800: Table 199. Rng Register Map And Reset Map
True random number generator (RNG) RM0440 25.7.4 RNG register map Table 199 gives the RNG register map and reset values. Table 199. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 801 RM0440 High-resolution timer (HRTIM) High-resolution timer (HRTIM) 26.1 Introduction The high-resolution timer can generate up to 12 digital signals with highly accurate timings. It is primarily intended to drive power conversion systems such as switch mode power supplies or lighting systems, but can be of general purpose usage, whenever a very fine timing resolution is expected.
Page 802 High-resolution timer (HRTIM) RM0440 26.2 Main features • High-resolution timing units – 184 ps resolution, compensated against voltage and temperature variations – High-resolution available on all outputs, possibility to adjust duty-cycle, frequency and pulse width in triggered one-pulse mode – 6 16-bit timing units (each one with an independent counter and 4 compare units) –...
Page 803 RM0440 High-resolution timer (HRTIM) 26.3 Functional description 26.3.1 General description The HRTIM can be partitioned into several sub entities: • The master timer • The timing units (timer A to timer F) • The output stage • The burst mode controller •...
Page 804: Figure 179. High-Resolution Timer Overview
High-resolution timer (HRTIM) RM0440 Note: As a writing convention, references to the 6 timing units in the text and in registers are generalized using the “x” letter, where x can be any value from A to F. The block diagram of the timer is shown in Figure 179.
Page 805: Table 200. Hrtim Inputs/Outputs Summary
RM0440 High-resolution timer (HRTIM) 26.3.2 HRTIM pins and internal signals The tables in this section summarize the HRTIM inputs and outputs, both on-chip and off- chip. Table 200. HRTIM inputs/outputs summary Signal name Signal type Description HRTIM_CHA1, HRTIM_CHA2, HRTIM_CHB1, HRTIM_CHB2, HRTIM_CHC1, HRTIM_CHC2, Main HRTIM timer outputs.
Page 806 High-resolution timer (HRTIM) RM0440 Table 200. HRTIM inputs/outputs summary (continued) Signal name Signal type Description hrtim_eev1[4:1] hrtim_eev2[4:1] hrtim_eev3[4:1] hrtim_eev4[4:1] External events. Each of the 10 events can be selected among 4 hrtim_eev5[4:1] sources, either on-chip (from other built-in peripherals: comparator, ADC Digital input analog watchdog, TIMx timers, trigger outputs) or off-chip hrtim_eev6[4:1]...
Page 807: Table 201. External Events Mapping And Associated Features
RM0440 High-resolution timer (HRTIM) Table 201. External events mapping and associated features Comparator and input sources Balanc Balanc Source (EExSRC[1:0]) available per External Fast Digital package event fault fault mode filter channel timer timer Src1 Src 2 Src3 Src4 64-pin and A,B,C D,E,F 48-pin...
Page 808: Table 204. Fault Inputs
High-resolution timer (HRTIM) RM0440 Table 204. Fault inputs External Input On-chip source External Input On-chip source Fault channel FLTxSRC[1:0] = FLTxSRC[1:0] = FLTxSRC[1:0] = FLTxSRC[1:0] = hrtim_in_flt1[4:1] PA12 COMP2 EEV1 hrtim_in_flt2[4:1] PA15 COMP4 EEV2 hrtim_in_flt3[4:1] PB10 COMP6 EEV3 hrtim_in_flt4[4:1] PB11 COMP1 EEV4 hrtim_in_flt5[4:1] PB0/PC7...
Page 809: Table 206. Timer Resolution And Min. Pwm Frequency For F
RM0440 High-resolution timer (HRTIM) deadtime generator clock. For convenience, only the t period (t ) is used in this document. chopper stage clock source. CHPFRQ clock source defining the length of the initial pulse in chopper mode. For 1STPW convenience, only the t period (t = 1/f ) is used in this...
Page 810: Figure 180. Counter And Capture Register Format Vs Clock Prescaling Factor
High-resolution timer (HRTIM) RM0440 Figure 180. Counter and capture register format vs clock prescaling factor Prescaling Significant bit: read returns effective value Not significant bit: read returns 0 MS32257V1 Initialization At start-up, it is mandatory to initialize first the prescaler bitfields before writing the compare and period registers.
Page 811 RM0440 High-resolution timer (HRTIM) Burst mode prescaler The burst mode controller counter clock f can be supplied by several sources, among BRST which one is derived from f HRTIM In this case, f ranges from f to f / 32768 (5.188 kHz for = 170 MHz).
Page 812: Figure 181. Timer A
High-resolution timer (HRTIM) RM0440 26.3.4 Timer A..F timing units The HRTIM embeds 6 identical timing units made of a 16-bit up-counter with an auto-reload mechanism to define the counting period, 4 compare and 2 capture units, as per Figure 181. Each unit includes all control features for 2 outputs, so that it operates as a standalone timer.
Page 813: Table 207. Period And Compare Registers Min And Max Values
RM0440 High-resolution timer (HRTIM) Table 207. Period and compare registers min and max values CKPSC[2:0] value 0x0060 0xFFDF 0x0030 0xFFEF 0x0018 0xFFF7 0x000C 0xFFFB 0x0006 0xFFFD ≥ 5 0x0003 0xFFFD 1. The value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse. See Section : Null duty cycle exception case for details.
Page 814: Figure 182. Continuous Timer Operation
High-resolution timer (HRTIM) RM0440 Figure 182. Continuous timer operation Counter Reset Enable Continuous mode (CONT = 1, RETRIG = X) MS32259V1 Figure 183. Single-shot timer operation PER event PER event Counter Reset* Enable Single-shot mode, non-retriggerable (CONT = 0, RETRIG = 0) PER event PER event Counter...
Page 815 RM0440 High-resolution timer (HRTIM) Roll-over event A counter roll-over event is generated when the counter goes back to 0 after having reached the period value set in the HRTIM_PERxR register in continuous mode. This event is used for multiple purposes in the HRTIM: –...
Page 816: Figure 184. Timer Reset Resynchronization (Prescaling Ratio Above 32)
High-resolution timer (HRTIM) RM0440 Figure 184. Timer reset resynchronization (prescaling ratio above 32) HRTIM Prescaled clock Reset event Counter Counter (PER = 5) HRTIM_CHA1 HRTIM_CHA1: Set on Timer A reset event, Reset on Compare 1 = 2 MS32261V2 Repetition counter A common software practice is to have an interrupt generated when the period value is reached, so that the maximum amount of time is left for processing before the next period begins.
Page 817: Figure 185. Repetition Rate Versus Hrtim_Repxr Content In Continuous Mode
RM0440 High-resolution timer (HRTIM) Figure 185. Repetition rate versus HRTIM_REPxR content in continuous mode Counter HRTIM_REPxR = 0 REP event HRTIM_REPxR = 1 HRTIM_REPxR = 2 * denotes repetition counter internal values (not readable, for explanation purpose only) MS32262V1 The repetition counter can also be used when the counter is reset before reaching the period value (variable frequency operation) either in continuous or in single-shot mode (Figure 186 here-below).
Page 818 High-resolution timer (HRTIM) RM0440 Set / reset crossbar A “set” event correspond to a transition to the output active state, while a “reset” event corresponds to a transition to the output inactive state. The polarity of the waveform is defined in the output stage to accommodate positive or negative logic external components: an active level corresponds to a logic level 1 for a positive polarity (POLx = 0), and to a logic level 0 for a negative polarity (POLx = 1).
Page 819: Table 209. Events Mapping Across Timer A To F
RM0440 High-resolution timer (HRTIM) Table 209. Events mapping across timer A to F Timer A Timer B Timer C Timer D Timer E Timer F Source Figure 187 represents how a PWM signal is generated using two compare events. Figure 187. Compare events action on outputs: set on compare 1, reset on compare 2 f HRTIM Clock Counter...
Page 820: Table 210. Interleaved Mode Selection
High-resolution timer (HRTIM) RM0440 This mode is enabled by writing HALF bit to 1 in the HRTIM_TIMxCR register. When the HRTIM_PERxR register is written, it causes an automatic update of the compare 1 value with HRTIM_PERxR/2 value. The output on which a square wave is generated must be programmed to have one transition on CMP1 event, and one transition on the period event, as follows: –...
Page 821: Table 211. Compare 1..3 Values In Interleaved Mode
RM0440 High-resolution timer (HRTIM) Table 211. Compare 1..3 values in interleaved mode Dual interleaved Triple interleaved Quad interleaved Mode 180° 120° 90° CMP1 value PERxR/2 PERxR/3 PERxR/4 CMP2 value Not affected 2x (PERxR/3) PERxR/2 CMP3 value Not affected Not affected 3x (PERxR/4) Note: In half and interleaved modes, the compare registers are controlled by hardware and writing...
Page 822 High-resolution timer (HRTIM) RM0440 Consequently, it does not modify the auxiliary outputs in parallel with the regular outputs going to the output stage (see Section 26.3.18 for details). They provide the following internal status, events and signals: – O1CPY, O2CPY, SETxy and RSTxy status flags, together with the corresponding interrupts and DMA requests –...
Page 823: Figure 188. Timer A Timing Unit Capture Circuitry
RM0440 High-resolution timer (HRTIM) Figure 188. Timer A timing unit capture circuitry CMP1 CMP2 Timer B TB1 set TB1 reset Timer C Capture 1 Timer D Trigger Timer E selection (OR) Capture 1 register Timer F External events 1..10 CPT1 Timer A Update (IRQ &...
Page 824: Figure 189. Auto-Delayed Overview (Compare 2 Only)
High-resolution timer (HRTIM) RM0440 Figure 189. Auto-delayed overview (compare 2 only) Capture 1 Counter Trigger: CPT1, DELCMP2[1..0] CMP1 or CMP3 Autodelayed Compare 2 Compare 2 DELCMP2[1..0] Compare 1 Compare 3 MS32266V1 The auto-delayed compare is only valid from the capture up to the period event: once the counter has reached the period value, the system is re-armed with compare disabled until a capture occurs.
Page 825: Figure 190. Auto-Delayed Compare
RM0440 High-resolution timer (HRTIM) match (DELCMPx[1:0]= 10) or a compare 3 match (DELCMPx[1:0]= 11) to have a timeout function if capture 1/2 event is missing. When the capture occurs, the comparison is done with the (HRTIM_CMP2/4xR + HRTIM_CPT1/2xR) value. If no capture is triggered within the period, the behavior depends on the DELCMPx[1:0] value: •...
Page 826 High-resolution timer (HRTIM) RM0440 A delayed compare is used for the output reset: the compare event can be generated only if a capture event has occurred. No event is generated when the counter matches the delayed compare value (counter = 4). Once the capture event has been triggered by the external event, the content of the capture register is summed to the delayed compare value to have the new compare value.
Page 827: Figure 191. Triggered-Half Mode Example
RM0440 High-resolution timer (HRTIM) have a master-slave system.The slave converter synchronization is continuously adjusted based on the previous switching period of the master converter. This is done using the capture unit. The switching period of the master converter is captured, divided by 2 and then stored in the compare 2 register by hardware. The compare 2 register contains a value equal to half of the captured period, which is the master converter switching period.
Page 828: Figure 192. Push-Pull Mode Block Diagram
High-resolution timer (HRTIM) RM0440 Note: In triggered half mode, the compare2 register is controlled by hardware and writing it has no effect. However the written value is stored in the preload register and becomes active on the update event following the exit of this mode. Push-pull mode This mode primarily aims at driving converters using push-pull topologies.
Page 829: Figure 193. Push-Pull Mode Example
RM0440 High-resolution timer (HRTIM) Figure 193. Push-pull mode example Period Counter Compare 1 Roll-over events Push-Pull logic Set on Reset on Crossbar output period compare 1 HRTIM_CHx1 HRTIM_CHx2 MS32269V2 Figure 194 shows how the deadtime is inserted in push-pull mode, for both positive and negative deadtimes.
Page 830: Figure 194. Push-Pull With Deadtime
High-resolution timer (HRTIM) RM0440 Figure 194. Push-Pull with deadtime Compare 2 Compare 1 Roll-over events Push-Pull logic Crossbar Set on output Period Reset HRTIM_CHx1 CMP1 Deadtime HRTIM_CHx2 rising Deadtime falling Crossbar Set on output Negative Period Deadtime Reset rising HRTIM_CHx1 CMP2 HRTIM_CHx2 Negative...
Page 831: Figure 195. Complementary Outputs With Deadtime Insertion
RM0440 High-resolution timer (HRTIM) Figure 195. Complementary outputs with deadtime insertion Counter Compare Crossbar output 1 Deadtime rising Deadtime falling HRTIM_CHx1 HRTIM_CHx2 MS32270V2 Negative deadtime values can be defined when some control overlap is required. This is done using the deadtime sign bits (SDTFx and SDTRx bits in HRTIM_DTxR register). Figure 196 shows complementary signal waveforms depending on respective signs.
Page 832: Table 212. Deadtime Resolution And Max Absolute Values
High-resolution timer (HRTIM) RM0440 Table 212 gives the resolution and maximum absolute values depending on the prescaler value. Table 212. Deadtime resolution and max absolute values = 170 MHz HRTIM DTPRSC[2:0] (ns) | max (µs) 0.73 0.38 HRTIM 1.47 0.75 HRTIM 2.94 1.50...
Page 833: Figure 199. Complementary Outputs For Low Pulsewidth (Sdtrx = 0, Sdtfx = 1)
RM0440 High-resolution timer (HRTIM) Figure 199. Complementary outputs for low pulsewidth (SDTRx = 0, SDTFx = 1) Ref. HRTIM_CHx1 HRTIM_CHx2 Deadtime falling Deadtime falling and rising skipped and rising skipped MS32274V3 Figure 200. Complementary outputs for low pulsewidth (SDTRx = 1, SDTFx=0) Ref.
Page 834: Figure 201. Master Timer Overview
High-resolution timer (HRTIM) RM0440 Figure 201 provides an overview of the master timer. Figure 201. Master timer overview Repetition External SYNC Synchronization Unit Counter Start Reset Counter Prescaler Period HRTIM CMP1 To Timer CMP2 CMP1 A..F CMP3 crossbars Compare 1 Half CMP4 SYNC...
Page 835: Figure 202. Basic Symmetric Waveform In Up-Down Counting Mode
RM0440 High-resolution timer (HRTIM) 26.3.6 Up-down counting mode The HRTIM is natively designed with up-counters. It offers however an operating mode with up-down counters, also called center-aligned mode. This mode is enabled using the UDM bit in the HRTIM_TIMxCR2 register. This bit must not be changed once the timer is operating (TxEN bit set).
Page 836: Figure 203. Complex Symmetric Waveform In Up-Down Counting Mode
High-resolution timer (HRTIM) RM0440 Figure 203 below shows how to generate some more complex waveforms, using the 4 available compare units and the toggle mode. Figure 203. Complex symmetric waveform in up-down counting mode Counter CMP4 CMP3 CMP2 CMP1 Set on CMP1 Set on CMP2 Reset on CMP3 Reset on CMP4...
Page 837: Figure 205. External Event Management In Up-Down Counting Mode
RM0440 High-resolution timer (HRTIM) The behavior of the software forcing bits and external events EXTEVNT1..10 is identical for up-only and up-down counting mode. The Figure 205 below shows how a pulse can be shorten in response to external events. Figure 205. External event management in up-down counting mode Counter CMP2 CMP1...
Page 838: Figure 207. Interleaved Up-Down Counter Operation
High-resolution timer (HRTIM) RM0440 Figure 207. Interleaved up-down counter operation TimA TimB HRTIM_CHx1 HRTIM_CHy1 Shorten pulse on TB1 on TimB counter reset MSv47420V2 Note: In up-down counting mode, the compare values must be 3 periods of the fHRTIM clock below the period value (TIMx_PER - 0xC0 if CKPSC[2:0] = 0, TIMx_PER - 0x60 if CKPSC[2:0] = 1, TIMx_PER - 0x30 if CKPSC[2:0] = 2,...).
Page 839: Table 213. Roll-Over Event Destination And Mode Programming
RM0440 High-resolution timer (HRTIM) Figure 209. Up-down mode with “greater than” comparison Set on CMP1 HRTIM_CHx1 MSv50805V1 Caution: The following features are not supported in up-down counting mode: - Auto-delayed mode - Balanced Idle - Triggered-half mode The capture function is supported with the following differences: –...
Page 840: Figure 210. Up-Down Mode With Output Set On Period Event, For Outrom[1:0]=10
High-resolution timer (HRTIM) RM0440 Note: For events where both reset and roll-over are considered (IRQ/DMA and TxRSTU), the ROM[1:0] only influences the roll-over generation. The reset event is always taken into account whatever the ROM[1:0] value. The roll-over event generation is defined as per following xxROM[1:0] bitfield setting: •...
Page 841: Table 214. Eexfltr[3:0] Codes Depending On Udm Bit Setting
RM0440 High-resolution timer (HRTIM) Figure 211 below shows how the repetition counter is decremented in up-down counting mode. Figure 211. Repetition counter behavior in up-down counting mode Counter REP = 0 ROM[1:0] = 00 REP = 0 ROM[1:0] = 01 REP = 0 ROM[1:0] = 10 REP = 1...
Page 842 High-resolution timer (HRTIM) RM0440 26.3.7 Set / reset events priorities and narrow pulses management This section describes how the output waveform is generated when several set and/or reset requests are occurring within 3 consecutive periods. HRTIM Case 1: clock prescaler CKPSC[2:0] < 5 An arbitration is performed during each t period, in 3 steps: HRTIM...
Page 843: Figure 212. Short Distance Set/Reset Management For Narrow Pulse Generation
RM0440 High-resolution timer (HRTIM) Figure 212. Short distance set/reset management for narrow pulse generation clock HRTIM Simulaneous set/reset Reset Set event is discarded Reset/set within the same period Set event is postponed if interval is < t HRTIM HRTIM Reset/set within Set event is anticipated if interval is >...
Page 844 High-resolution timer (HRTIM) RM0440 If the set and reset events are generated with an interval above 3 periods, the high- HRTIM resolution is always available. Concurrent set requests/ Concurrent reset requests When multiple sources are selected for a set event, an arbitration is performed when the set requests occur within the same f clock period.
Page 845 RM0440 High-resolution timer (HRTIM) If a reset event is followed by a set event within the same prescaler clock cycle, the latest event is considered. 26.3.8 External events global conditioning The HRTIM timer can handle events not generated within the timer, referred to as “external event”.
Page 846: Figure 213. External Event Conditioning Overview (1 Channel Represented)
High-resolution timer (HRTIM) RM0440 Figure 213. External event conditioning overview (1 channel represented) Output Timer A..E Output stage Timer A..E Output stage Timer A..E Output stage Timer A..E Output stage Timer A..F stage Other EEVNT channels Synchronous EEVx_muxout path EExPOL (to FAULT circuitry) EExFAST = 0 hrtim_eevx[4:1]...
Page 847: Table 215. External Events Features
RM0440 High-resolution timer (HRTIM) transmitted as a correct external event. Consequently, the digital filter adds a latency to the external events being filtered, depending on the sampling clock and on the filter length (number of valid samples expected). The sampling clock is either the f clock or a specific prescaled clock f derived HRTIM...
Page 848: Table 216. Output Set/Reset Latency And Jitter Versus External Event Operating Mode
High-resolution timer (HRTIM) RM0440 Table 216. Output set/reset latency and jitter versus external event operating mode Response time Jitter on output pulse EExFAST Response time jitter latency (counter reset by ext. event) 5 to 6 cycles of f 1 cycles of f No jitter, pulse width maintained with HRTIM HRTIM...
Page 849: Figure 214. Latency To External Events Falling Edge (Counter Reset And Output Set)
RM0440 High-resolution timer (HRTIM) Figure 214. Latency to external events falling edge (counter reset and output set) clock HRTIM External Event 2-3 cycles delay External Event after internal Counter reset re-synchronisation HRTIMER 1190 11A0 11C0 1200 1220 1240 counter 3 cycles delay HRTIMER output EExFAST = 0...
Page 850: Figure 216. Event Blanking Mode
High-resolution timer (HRTIM) RM0440 26.3.9 External event filtering in timing units Once conditioned, the 10 external events are available for all timing units. They can be used directly and are active as soon as the timing unit counter is enabled (TxCEN bit set).
Page 851: Table 217. Filtering Signals Mapping Per Timer
RM0440 High-resolution timer (HRTIM) The blanking signal comes from several sources: • the timer itself: the blanking lasts from the counter reset to the compare match (EExFLTR[3:0] = 0001 to 0100 for compare 1 to compare 4). In up/down mode (UDM bit set to 1), the counter reset event is defined as per the ROM[1:0] bit setting.
Page 852: Figure 218. External Trigger Blanking With Edge-Sensitive Trigger
High-resolution timer (HRTIM) RM0440 Figure 218. External trigger blanking with edge-sensitive trigger Counter Compare 1 Blanking window External event EExLTCH = 0 EExLTCH = 1 EExSNS[1:0] = 01 EExSNS[1:0] = 10 EExSNS[1:0] = 11 Internal event generated after blanking MS32296V2 Figure 219.
Page 853: Table 218. Windowing Signals Mapping Per Timer (Eefltr[3:0] = 1111)
RM0440 High-resolution timer (HRTIM) Windowing mode In event windowing mode, the event is taken into account only if it occurs within a given time window, otherwise it is ignored. This mode is active for EExFLTR[3:0] ranging from 1101 to 1111. Figure 220.
Page 854: Figure 221. External Trigger Windowing With Edge-Sensitive Trigger
High-resolution timer (HRTIM) RM0440 Figure 221. External trigger windowing with edge-sensitive trigger Counter Compare 1 Window External event (Timeout) EExLTCH = 0 (Timeout) (Timeout) EExLTCH = 1 EExSNS[1:0] = 01 EExSNS[1:0] = 10 EExSNS[1:0] = 11 Internal event generated after windowing MS32299V2 Figure 222.
Page 855: Figure 223. External Event Counter - Channel A
RM0440 High-resolution timer (HRTIM) External event counter Each timing unit also features an external event counter following the filtering unit, typically for valley skipping implementation. The circuitry allows to filter any of the 10 external events filtered, as shown on Figure 223.
Page 856: Figure 224. External Event Counter Cumulative Mode (Eevxrstm = 1, Eevxcnt = 2)
High-resolution timer (HRTIM) RM0440 Figure 224. External event counter cumulative mode (EEVxRSTM = 1, EEVxCNT = 2) Counter EEV input EEV edge detector EEV counter EEV event PWM output MSv47423V2 26.3.10 Delayed protection The HRTIM features specific protection schemes, typically for resonant converters when it is necessary to shut down the PWM outputs in a delayed manner, either once the active pulse is completed or once a push-pull period is completed.
Page 857: Figure 225. Delayed Idle Mode Entry
RM0440 High-resolution timer (HRTIM) idle is applied to a single output. When the push-pull mode is enabled, the IPPSTAT flag in HRTIM_TIMxISR indicates during which period the delayed protection request occurred. This mode is available whatever the timer operating mode (regular, push-pull, deadtime). It is available with 2 external events only: •...
Page 858: Figure 226. Burst Mode And Delayed Protection Priorities (Didl = 0)
High-resolution timer (HRTIM) RM0440 Figure 226. Burst mode and delayed protection priorities (DIDL = 0) Delayed protection Delayed protection Entry (discarded, burst exit (discarded, burst has priority) has priority) Burst exit Burst entry Output State IDLE Burst exit (discarded, delayed protection has priority) Burst entry Delayed...
Page 859: Figure 227. Burst Mode And Delayed Protection Priorities (Didl = 1)
RM0440 High-resolution timer (HRTIM) Figure 227. Burst mode and delayed protection priorities (DIDL = 1) Burst exit Delayed protection Delayed Burst entry protection exit Crossbar output IDLES level Output Deadtime Burst exit Burst entry Delayed Delayed protection protection exit Crossbar output IDLES level Output...
Page 860: Figure 228. Balanced Idle Protection Example
High-resolution timer (HRTIM) RM0440 Figure 228. Balanced Idle protection example counter CMP1 Taref (internal) HRTIM_CHx1 HRTIM_CHx2 CPPSTAT = 0 CPPSTAT = 1 CPPSTAT = 0 CPPSTAT = 1 HRTIM_CHx1 Pulse length copied HRTIM_CHx2 IPPSTAT = 0 HRTIM_CHx1 Pulse length copied HRTIM_CHx2 IPPSTAT = 0 (reset value) IPPSTAT = 1...
Page 861 RM0440 High-resolution timer (HRTIM) while the IPPSTAT flag indicates during which period the external event occurred, to determine the sequence of shorten pulses (A1 then A2 or vice versa). The timer operation is not interrupted (the counter continues to run). To enable the balanced idle mode, it is necessary to have the following initialization: –...
Page 862 High-resolution timer (HRTIM) RM0440 The balanced idle mode has a higher priority than the burst mode: any burst mode exit request is discarded once the balanced idle protection has been triggered. On the contrary, if the delayed protection is exited while the burst mode is active, the burst mode is resumed normally.
Page 863: Table 219. Hrtim Preloadable Control Registers And Associated Update Sources
RM0440 High-resolution timer (HRTIM) Table 219 lists the registers which can be preloaded, together with a summary of available update events. Table 219. HRTIM preloadable control registers and associated update sources Timer Preloadable registers Preload enable Update sources HRTIM_DIER HRTIM_MPER Software HRTIM_MREP Repetition event...
Page 864 High-resolution timer (HRTIM) RM0440 Each timer (TIMA..F) can also have the update done as follows: • By software: writing 1 into TxSWU bit in HRTIM_CR2 forces an immediate update of the registers. In this case, any pending hardware update request is canceled. •...
Page 865: Figure 229. Resynchronized Timer Update (Tau=1 In Hrtim_Timbcr)
RM0440 High-resolution timer (HRTIM) Figure 229. Resynchronized timer update (TAU=1 in HRTIM_TIMBCR) TIMA Counter HRTIM_CHx1 TIMA update RSYNCU=0 TIMB update RSYNCU=1 TIMB Counter HRTIM_CHy1 MSv47432V2 MUDIS and TxUDIS bits in the HRTIM_CR1 register allow to temporarily disable the transfer from preload to active registers, whatever the selected update event. This allows to modify several registers in multiple timers.
Page 866 High-resolution timer (HRTIM) RM0440 When the power converter set-point has to be adjusted by software, TAUDIS, TDUDIS and TEUDIS bits of the HRTIM_CR register must be set prior to write accessing the registers to update the values (for instance the compare values). From this time on, any hardware update request is ignored and the preload registers can be accessed without any risk to have them transferred into the active registers.
Page 867: Figure 230. Early Turn-On And Early Turn-Off Behavior In "Greater Than" Pwm Mode
RM0440 High-resolution timer (HRTIM) In the fixed frequency configuration, the period event must trigger the output set and the “greater than” compare triggers the output reset (or vice versa the period must trigger the reset if the “greater-than” compare triggers the set). For variable frequency configuration, the event selected as counter reset source must also be selected as set or reset source for the timer output (opposite direction as the “greater than”...
Page 868: Table 220. Master Timer Update Event Propagation
High-resolution timer (HRTIM) RM0440 TIMx update triggered by the master timer update The sources listed in Table 220 are generating a master timer update. The table indicates if the source event can be used to trigger a simultaneous update in any of TIMx timing units. Operating condition: MSTU bit is set in HRTIM_TIMxCR register.
Page 869 RM0440 High-resolution timer (HRTIM) Table 221. TIMx update event propagation (continued) Source Condition Propagation Comment TyRST=1 in Can be done simultaneously with update in Counter software reset HRTIM_CR2 HRTIM_CR2 register Counter reset caused TIMzCMPn in by a TIMz compare HRTIM_RSTyR Counter reset caused EXTEVNTn in by external events...
Page 870: Table 222. Reset Events Able To Generate An Update
High-resolution timer (HRTIM) RM0440 TIMx counter reset causing a TIMx update Table 222 lists the counter reset sources and indicates whether they can be used to generate an update. Operating condition: TxRSTU bit in HRTIM_TIMxCR register. Table 222. Reset events able to generate an update Source Condition Propagation...
Page 871 RM0440 High-resolution timer (HRTIM) Table 223. Update event propagation for a timer reset (continued) Source Condition Propagation Comment Master update caused by a repetition event following a MSTU = 1 in roll-over HRTIM_TIMxCR Master update caused by a MREPU = 1 in repetition event following a HRTIM_MCR counter reset (software or...
Page 872: Table 224. Output State Programming, X= A..f, Y = 1 Or 2
High-resolution timer (HRTIM) RM0440 26.3.14 Output management Each timing unit controls a pair of outputs. The outputs have three operating states: • RUN: this is the main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit. •...
Page 873: Figure 232. Hrtim Output States And Transitions
RM0440 High-resolution timer (HRTIM) Section 26.3.17, while the Idle state can be entered when the burst mode or delayed protections are active. Figure 232. HRTIM output states and transitions IDLE State OEN = 0 ODS = 0 (Fault or breakpoint*) &...
Page 874: Figure 233. Burst Mode Operation Example
High-resolution timer (HRTIM) RM0440 The level of the output in IDLE state is configured using IDLESx bit in HRTIM_OUTxR, as follows: • 0: output at inactive level when in IDLE • 1: output at active level when in IDLE When TxyOEN bit is set to enter the RUN state, the output is immediately connected to the crossbar output.
Page 875: Table 225. Timer Output Programming For Burst Mode
RM0440 High-resolution timer (HRTIM) The burst mode controller is able to take over the control of any of the 10 PWM outputs. The state of each output during a burst mode operation is programmed using IDLESx and IDLEMx bits in the HRTIM_OUTxR register, as in Table 225.
Page 876 High-resolution timer (HRTIM) RM0440 start or timer A start), a pulse is sent on the HRTIM_SCOUT output when exiting the burst mode. Note: TxBM bit must not be set when the balanced idle mode is active (DLYPRT[1:0] = 0x11). Burst mode clock The burst mode controller counter can be clocked by several sources, selected with BMCLK[3:0] bits in the HRTIM_BMCR register: •...
Page 877: Figure 234. Burst Mode Trigger On External Event
RM0440 High-resolution timer (HRTIM) Figure 234. Burst mode trigger on external event External event Counter Output Trigger on Output external event IDLE state Output Trigger on timer period following Output IDLE external event state MS32284V1 For TAEEV7 and TDEEV8 combined triggers (trigger on a timer period following an external event), the external event detection is always active, regardless of the burst mode programming and the on-going burst operation: •...
Page 878: Figure 235. Delayed Burst Mode Entry With Deadtime Enabled And Idlesx = 1
High-resolution timer (HRTIM) RM0440 Figure 235. Delayed burst mode entry with deadtime enabled and IDLESx = 1 Burst Trigger Output State IDLE HRTIM_CHx1 IDLES1 = 1 DIDL1 = 0 Deadtime DIDL2 = 0 violation HRTIM_CHx2 IDLES2 = 0 HRTIM_CHx1 IDLES1 = 1 DIDL1 = 1 Delayed idle DIDL2 = 1...
Page 879: Figure 236. Delayed Burst Mode Entry During Deadtime
RM0440 High-resolution timer (HRTIM) Figure 236. Delayed burst mode entry during deadtime Burst mode entry IDLES HRTIM_CHx1 HRTIM_CHx2 IDLES Regular deadtime (aborted when burst is triggered) Delayed Burst mode entry deadtime MS32286V3 Burst mode exit The burst mode exit is either forced by software (in continuous mode) or once the idle period is elapsed (in single-shot mode).
Page 880: Figure 237. Burst Mode Exit When The Deadtime Generator Is Enabled
High-resolution timer (HRTIM) RM0440 Figure 237. Burst mode exit when the deadtime generator is enabled Timx counter Out1 crossbar waveform Burst state IDLE HRTIM_CHx1 HRTIM_CHx2 Burst state IDLE HRTIM_CHx1 HRTIM_CHx2 MS32287V3 The behavior described above is slightly different when the push-pull mode is enabled. The push-pull mode forces an output reset at the beginning of the period if the output is inactive, or symmetrically forces an active level if the output was high during the preceding period.
Page 881 RM0440 High-resolution timer (HRTIM) When BMPREN bits is reset, the write access into BMCMPR and BMPER directly updates the active register. In this case, it is necessary to consider when the update is done during the overall burst period, for the 2 cases below: Compare register update If the new compare value is above the current burst mode counter value, the new compare is taken into account in the current period.
Page 882: Figure 238. Burst Mode Emulation Example
High-resolution timer (HRTIM) RM0440 Figure 238. Burst mode emulation example Counter request request request request CMPC1xR 0x0001 0800 0x0003 0000 0x0001 0800 Output REPxR =1 REPxR =3 REPxR =1 CMP1xR = 0x0800 CMP1xR = 0x0000 CMP1xR = 0x0800 IDLE (emulated) MS32288V1 26.3.16 Chopper...
Page 883: Figure 240. Hrtim Outputs With Chopper Mode Enabled
RM0440 High-resolution timer (HRTIM) The chopper parameters can be adjusted using the HRIM_CHPxR register, with the possibility to define a specific pulsewidth at the beginning of the pulse, to be followed by a carrier frequency with programmable frequency and duty cycle, as in Figure 240.
Page 884: Table 226. Fault Inputs
High-resolution timer (HRTIM) RM0440 Figure 241. Fault protection circuitry (FAULT1 fully represented, FAULT2..6 partially) FAULT1[1:0] FAULT2[1:0] HRTIM_CHx1 Timer x HRTIM_CHx2 FLT1RSTM FLT1CRES Counter FLT1P FLT1CNT[3:0] FLT1SRC[1:0] FLT1P Fault 6 FLT1F[3:0] FLTS FLT1CNT[3:0] Fault 5 Fault 4 EEV1_muxout FLT1 Filter HRTIM_FLT[1] FLT1E Polarity Fault2...
Page 885: Sampling = Fhrtim, N = 4)
RM0440 High-resolution timer (HRTIM) The EEVx_muxout event mentioned in Table 226 above is taken after the hrtim_eevx[4:1] input multiplexer controlled by the EExSRC[1:0]bits. Refer to Figure 213 for details. The polarity of the signal can be selected to define the active level, using the FLTxP polarity bit in HRTIM_FLTINRx registers.
Page 886: Table 227. Sampling Rate And Filter Length Vs Fltfxf[3:0] And Clock Setting
High-resolution timer (HRTIM) RM0440 Table 227. Sampling rate and filter length vs FLTFxF[3:0] and clock setting vs FLTSD[1:0] Filter length for f = 170 MHz FLTS HRTIM FLTFxF[3:0] , N =2 , N =8 HRTIM HRTIM 0001,0010,0011 HRTIM HRTIM HRTIM HRTIM 11.8 ns 47.1 ns...
Page 887: Table 229. Fault 1..6 Counter Reset Source
RM0440 High-resolution timer (HRTIM) Figure 243. Fault counter cumulative mode (FLTxRSTM = 1, FLTxCNT[3:0] = 2) Counter FLT input FLT edge detector FLT counter FLT event PWM output MSv47426V1 A given FLTx input counter can be reset by a single source. The Table 229 indicates which timer unit associated with a given fault.
Page 888 High-resolution timer (HRTIM) RM0440 For each FAULT channel, a write-once FLTxLCK bit in the HRTIM_FLTxR register allows to lock FLTxE, FLTxP, FLTxSRC, FLTxF[3:0] bits (it renders them read-only), for functional safety purpose. If enabled, the fault conditioning set-up is frozen until the next HRTIM or system reset.
Page 889: Figure 244. Auxiliary Outputs
RM0440 High-resolution timer (HRTIM) Figure 244. Auxiliary outputs Out 1 HRTIM_CHx1 Push-pull Set / reset To the Burst mode crossbar with output deadtime controller events ORing stage insertion HRTIM_CHx2 Out 2 Auxiliary output circuitry SETxy / RSTxy flags Interrupts and DMA requests Capture triggers External event filtering (Out 2 channel only)
Page 890: Figure 245. Auxiliary And Main Outputs During Burst Mode (Didlx = 0)
High-resolution timer (HRTIM) RM0440 Figure 245. Auxiliary and main outputs during burst mode (DIDLx = 0) Burst mode Burst mode entry exit Auxiliary output1 Auxiliary output2 HRTIM_CHx1 IDLES level HRTIM_CHx2 IDLES level IDLES level continued up to the transition to the opposite level MS32291V2 The signal on the auxiliary output can be slightly distorted when exiting from the burst mode...
Page 891 RM0440 High-resolution timer (HRTIM) 26.3.19 Synchronizing the HRTIM with other timers or HRTIM instances The HRTIM provides options for synchronizing multiple HRTIM instances, as a master unit (generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized). This feature can also be used to synchronize the HRTIM with other timers, either external or on-chip.
Page 892: Table 230. Effect Of Sync Event Versus Timer Operating Modes
High-resolution timer (HRTIM) RM0440 Synchronization input The HRTIM can be synchronized by external sources, as per the programming of the SYNCIN[1:0] bits in the HRTIM_MCR register: • 00: synchronization input is disabled • 01: reserved configuration • 10: the On-chip timer TRGO output connected to hrtim_in_sync[2] input (refer to Table 200 for details).
Page 893 RM0440 High-resolution timer (HRTIM) Table 230. Effect of sync event versus timer operating modes (continued) SYNC SYNC Operating mode Behavior following a SYNC reset or start event RSTx STRTx The counter start is effective only if the counter is not started or period is elapsed.
Page 894: Figure 247. Counter Behavior In Synchronized Start Mode
High-resolution timer (HRTIM) RM0440 Figure 247 presents how the synchronized start is done in single-shot mode. Figure 247. Counter behavior in synchronized start mode Counter initialized by software Counter SCIN Internal reset request SYNCSTRT, Single-shot mode, non-retriggerable Counter initialized by software Counter SCIN Internal reset...
Page 895: Figure 248. Adc Trigger Selection Overview
RM0440 High-resolution timer (HRTIM) Figure 248. ADC trigger selection overview hrtim_adc hrtim_adc hrtim_adc hrtim_adc _trg1 _trg3 _trg2 _trg4 Master Cmp1..4 + PER Master Cmp1..4 + PER External Events 1..5 External Events 6..10 TimerA Cmp3,4 + PER + RST TimerA Cmp2,4 + PER TimerB Cmp2,4 + PER TimerB Cmp3,4 + PER + RST Trigger 1...
Page 896: Figure 249. Adc Triggers
High-resolution timer (HRTIM) RM0440 Figure 249. ADC triggers hrtim_adc hrtim_adc hrtim_adc hrtim_adc hrtim_adc hrtim_adc _trg5 _trg7 _trg9 _trg6 _trg8 _trg10 Master Cmp1,2,3,4 + PER Master Cmp1,2,3,4 + PER External Events 1..5 External Events 6..10 TimerA Cmp3,4 + PER + RST TimerA Cmp2,4 + PER TimerB Cmp2,4 + PER TimerB Cmp3,4 + PER + RST...
Page 897: Figure 250. Adc Trigger Post-Scaling In Up-Counting Mode
RM0440 High-resolution timer (HRTIM) The ADC post-scaler programming register are preloaded and can be updated on-the-fly without stopping the timers. Figure 250. ADC trigger post-scaling in up-counting mode Counter ADCxPSC[4:0]=0 ADCxPSC[4:0]=1 ADCxPSC[4:0]=2 ADCxPSC[4:0]=3 ADCxPSC[4:0]=4 MSv47427V1 Figure 251. ADC trigger post-scaling in up/down counting mode Counter ADCxPSC[4:0]=0 ADROM[1:0]=00...
Page 898: Figure 252. Combining Several Updates On A Single Hrtim_Dac_Trgx Output
High-resolution timer (HRTIM) RM0440 26.3.21 DAC triggers The HRTIM allows to have the embedded DACs updated synchronously with the timer updates. The update events from the master timer and the timer units can generate DAC update triggers on any of the 3 hrtim_dac_trgx outputs. Note: Each timer has its own DAC-related control register.
Page 899 RM0440 High-resolution timer (HRTIM) Dual channel DAC trigger Slope compensation techniques and hysteretic control to be easily implemented using HRTIM built-in features and the DAC sawtooth generator. The principle is to have a DAC generating a decreasing saw-tooth synchronized with the PWM period, or a square wave synchronized with PWM signal.
Page 900: Table 231. Dac Dual Channel Trigger Example
High-resolution timer (HRTIM) RM0440 Table 231 below gives an example, for generating 6 triggers within a PWM period. It shows that it is necessary to round up the division result to the upper value. Let’s consider a counter period TIMxPER = 8192. Dividing 8192 by 6 yields 1365.33. –...
Page 901: Figure 253. Dac Triggers For Slope Compensation
RM0440 High-resolution timer (HRTIM) Figure 253. DAC triggers for slope compensation CMP1 CMP2 Output 1 hrtim_dac_reset_trigx hrtim_dac_step_trigx DAC output DCDR = 0 (reset on roll-over), DCDT = 0 (step trigger on Compare 2) CMP1 CMP2 Output 1 hrtim_dac_reset_trigx hrtim_dac_step_trigx DAC output DCDR = 1 (reset on output 1 set), DCDT = 1 (step trigger on output 1 reset) MSv47433V1 RM0440 Rev 1...
Page 902: Figure 254. Dac Triggers Overview
High-resolution timer (HRTIM) RM0440 Figure 254 below provides an overview of all the available DAC triggers. Figure 254. DAC triggers overview Master TimA TimB TimC TimD TimE TimF DACSYNC DACSYNC DACSYNC DACSYNC DACSYNC DACSYNC DACSYNC [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] dac_trig_out1...
Page 903: Table 232. Hrtim Interrupt Summary
RM0440 High-resolution timer (HRTIM) 14 interrupts can be generated by each timing unit: • Delayed protection triggered • Counter reset or roll-over event • Output 1 and output 2 reset (transition active to inactive) • Output 1 and output 2 set (transition inactive to active) •...
Page 904 High-resolution timer (HRTIM) RM0440 Table 232. HRTIM interrupt summary (continued) Interrupt Enable Flag clearing Interrupt event Event flag vector control bit Delayed protection triggered DLYPRT DLYPRTIE DLYPRTC Counter reset or roll-over event RSTIE RSTC RSTx1 RSTx1IE RSTx1C Output 1 and output 2 reset (transition active to inactive) RSTx2 RSTx2IE...
Page 905: Table 233. Hrtim Dma Request Summary
RM0440 High-resolution timer (HRTIM) Table 233. HRTIM DMA request summary DMA enable DMA Channel Event capable Burst mode period completed DLL calibration done Master timer registers update MUPDDE Synchronization event received SYNCDE hrtim_dma1 Master timer repetition event MREPDE (master timer) MCMP1DE MCMP2DE Master compare 1 to 4 event...
Page 906: Figure 255. Dma Burst Overview
High-resolution timer (HRTIM) RM0440 The burst DMA feature is only available for one DMA channel, but any of the 6 channels can be selected for burst DMA transfers. The principle is to program which registers are to be written by DMA. The master timer and TIMA..E have the burst DMA update register, where most of their control and data registers are associated with a selection bit: HRTIM_BDMUPR, HRTIM_BDTAUPR to HRTIM_BDTEUPR (this is applicable only for registers with write accesses).
Page 907: Figure 256. Burst Dma Operation Flowchart
RM0440 High-resolution timer (HRTIM) Figure 256. Burst DMA operation flowchart Write access to HRTIM_BDMADR Parse Parse Parse HRTIM_BDMUPR HRTIM_BDTAUPR HRTIM_BDTFUPR Write data into Write data into Write data into TIMACR bit TIMFCR bit MCR bit set? set? set? HRTIM_MCR HRTIM_TIMACR HRTIM_TIMFCR Write data into Write data into...
Page 908: Figure 257. Registers Update Following Dma Burst Transfer
High-resolution timer (HRTIM) RM0440 The chronogram on Figure 257 presents the active register content for 3 cases: PREEN=0, UPDGAT[3:0] = 0001 and UPDGAT[3:0] = 0001 (when PREEN = 1). Figure 257. Registers update following DMA burst transfer DMA request on CMP1 event starts DMA burst Timer A Counter...
Page 909 RM0440 High-resolution timer (HRTIM) The HRTIM control registers can be initialized as per the power converter topology and the timing units use case. All inputs have to be configured (source, polarity, edge-sensitivity). The HRTIM outputs must be set up eventually, with the following sequence: •...
Page 910: Figure 258. Buck Converter Topology
High-resolution timer (HRTIM) RM0440 Synchronization, counter reset, start and reset-start events are discarded in debug mode, as well as capture events. This is to keep all related registers stable as long as the MCU is halted. The counter stops counting when a breakpoint is reached. However, the counter enable signal is not reset;...
Page 911: Figure 259. Dual Buck Converter Management
RM0440 High-resolution timer (HRTIM) Figure 259. Dual Buck converter management CMP4 TIMA CMP3 counter CMP2 CMP1 TIMA HRTIM_CHA1 outputs (BUCK 1) HRTIM_CHA2 (BUCK 2) MS32344V2 Timers A..E provide either 12 buck converters coupled by pairs (both with identical switching frequencies) or 7 completely independent converters (each of them having a different switching frequency), using the master timer as the 7 time base.
Page 912: Figure 261. Buck With Synchronous Rectification
High-resolution timer (HRTIM) RM0440 Figure 261. Buck with synchronous rectification TIMA counter CMP2 CMP1 HRTIM_CHA1 TIMA outputs HRTIM_CHA2 Synchronous Rectification (SR) active SR disabled MS32346V2 26.4.3 Multiphase converters Multiphase techniques can be applied to multiple power conversion topologies (buck, flyback). Their main benefits are: •...
Page 913: Figure 263. 3-Phase Interleaved Buck Converter Control
RM0440 High-resolution timer (HRTIM) The master timer is responsible for the phase management: it defines the phase relationship between the converters by resetting the timers periodically. The phase-shift is 360° divided by the number of phases, 120° in the given example. The duty cycle is then programmed into each of the timers.
Page 914: Figure 264. Transition Mode Pfc
High-resolution timer (HRTIM) RM0440 Figure 264. Transition mode PFC HRTIM_ CHA2 MS32349V3 This converter operates with a constant Ton time and a variable frequency due the Toff time variation (depending on the input voltage). It must also include some features to operate when no zero-crossing is detected, or to limit the Ton time in case of over-current (OC).
Page 915: Figure 265. Transition Mode Pfc Waveforms
RM0440 High-resolution timer (HRTIM) Figure 265. Transition mode PFC waveforms CMP4 CMP1 Zero Current Detection (ZCD) ZCD blanking OverCurrent (OC) OC blanking HRTIM_ CHA1 Normal operation Over Current Toff Min Toff Max Normal operation Capture event MS32350V2 RM0440 Rev 1 915/2083 1040...
Page 916 High-resolution timer (HRTIM) RM0440 26.5 HRTIM registers 26.5.1 HRTIM master timer control register (HRTIM_MCR) Address offset: 0x000 Reset value: 0x0000 0000 MREP BRSTDMA[1:0] Res. PREEN DACSYNC[1:0] Res. Res. TFCEN TECEN TDCEN TCCEN TBCEN TACEN MCEN SYNCS SYNCR SYNCSRC[1:0] SYNCOUT[1:0] SYNCIN[1:0] INTLVD[1:0] HALF CONT...
Page 917 RM0440 High-resolution timer (HRTIM) Bit 21 TECEN: Timer E counter enable This bit starts the timer E counter. 0: Timer E counter disabled 1: Timer E counter enabled Note: This bit must not be changed within a minimum of 8 cycles of f clock.
Page 918 High-resolution timer (HRTIM) RM0440 Bit 10 SYNCRSTM: Synchronization resets master This bit enables the master timer reset when receiving a synchronization input event: 0: No effect on the master timer 1: A synchronization input event resets the master timer Bits 9:8 SYNCIN[1:0] Synchronization input These bits are defining the synchronization input source.
Page 919 RM0440 High-resolution timer (HRTIM) 26.5.2 HRTIM master timer interrupt status register (HRTIM_MISR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCMP MCMP MCMP MCMP Res. Res.
Page 920 High-resolution timer (HRTIM) RM0440 26.5.3 HRTIM master timer interrupt clear register (HRTIM_MICR) Address offset: 0x008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MUPD MREP MCMP MCMP MCMP MCMP Res.
Page 921 RM0440 High-resolution timer (HRTIM) 26.5.4 HRTIM master timer DMA interrupt enable register (HRTIM_MDIER) Address offset: 0x00C Reset value: 0x0000 0000 MUPD SYNCD MREP MCMP MCMP MCMP MCMP Res. Res. Res. Res. Res. Res. Res. Res. Res. MUPDI SYNCI MREPI MCMP MCMP MCMP MCMP...
Page 922 High-resolution timer (HRTIM) RM0440 Bit 4 MREPIE: Master repetition interrupt enable This bit is set and cleared by software to enable/disable the master timer repetition interrupts 0: Master repetition interrupt disabled 1: Master repetition interrupt enabled Bit 3 MCMP4IE: Master compare 4 interrupt enable Refer to MCMP1IE description Bit 2 MCMP3IE: Master compare 3 interrupt enable Refer to MCMP1IE description...
Page 923 RM0440 High-resolution timer (HRTIM) 26.5.5 HRTIM master timer counter register (HRTIM_MCNTR) Address offset: 0x010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCNT[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCNT[15:0]: Counter value Holds the master timer counter value.
Page 924 High-resolution timer (HRTIM) RM0440 26.5.7 HRTIM master timer repetition register (HRTIM_MREP) Address offset: 0x018 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 925 RM0440 High-resolution timer (HRTIM) 26.5.9 HRTIM master timer compare 2 register (HRTIM_MCMP2R) Address offset: 0x024 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCMP2[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP2[15:0]: Master timer compare 2 value This register holds the master timer compare 2 value.
Page 926 High-resolution timer (HRTIM) RM0440 26.5.11 HRTIM master timer compare 4 register (HRTIM_MCMP4R) Address offset: 0x02C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCMP4[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP4[15:0]: Master timer compare 4 value This register holds the master timer compare 4 value.
Page 927 RM0440 High-resolution timer (HRTIM) 26.5.12 HRTIM timer x control register (HRTIM_TIMxCR) (x = A to F) Address offset: Block A: 0x080 Address offset: Block B: 0x100 Address offset: Block C: 0x180 Address offset: Block D: 0x200 Address offset: Block E: 0x280 Address offset: Block F: 0x300 Reset value: 0x0000 0000 TxRST...
Page 928 High-resolution timer (HRTIM) RM0440 Bits 31:28 UPDGAT[3:0]: Update gating These bits define how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs hrtim_upd_en[3:1] (see Table 202). The update events, as mentioned below, can be: MSTU, TFU, TEU, TDU, TCU, TBU, TAU, TxRSTU, TxREPU.
Page 929 RM0440 High-resolution timer (HRTIM) Bit 21 TCU: Timer C update Register update is triggered by the timer C update 0: Update by timer C disabled 1: Update by timer C enabled Note: This bit is reserved for HRTIM_TIMCCR. It is only available for HRTIM_TIMACR, HRTIM_TIMBCR, HRTIM_TIMDCR, HRTIM_TIMECR, HRTIM_TIMFCR.
Page 930 High-resolution timer (HRTIM) RM0440 Bits 13:12 DELCMP2[1:0]: CMP2 auto-delayed mode This bitfield defines whether the compare register is behaving in standard mode (compare match issued as soon as counter equal compare), or in auto-delayed mode (see Section : Auto-delayed mode). 00: CMP2 register is always active (standard compare mode) 01: CMP2 value is recomputed and is active following a capture 1 event 10: CMP2 value is recomputed and is active following a capture 1 event, or is recomputed and...
Page 931 RM0440 High-resolution timer (HRTIM) Bit 4 RETRIG: Re-triggerable mode This bit defines the counter behavior in single shot mode. 0: The timer is not re-triggerable: a counter reset is done if the counter is stopped (period elapsed in single-shot mode or counter stopped in continuous mode) 1: The timer is re-triggerable: a counter reset is done whatever the counter state.
Page 932 High-resolution timer (HRTIM) RM0440 26.5.13 HRTIM timer x interrupt status register (HRTIM_TIMxISR) (x = A to F) Address offset: Block A: 0x084 Address offset: Block B: 0x104 Address offset: Block C: 0x184 Address offset: Block D: 0x204 Address offset: Block E: 0x284 Address offset: Block F: 0x304 Reset value: 0x000 0000 Res.
Page 933 RM0440 High-resolution timer (HRTIM) Bit 16 CPPSTAT: Current push-pull status This status bit indicates on which output the signal is currently applied, in push-pull mode. It is only significant in this configuration. 0: Signal applied on output 1 and output 2 forced inactive 1: Signal applied on output 2 and output 1 forced inactive Bit 15 Reserved, must be kept at reset value.
Page 934 High-resolution timer (HRTIM) RM0440 Bit 2 CMP3: Compare 3 interrupt flag Refer to CMP1 description Bit 1 CMP2: Compare 2 interrupt flag Refer to CMP1 description Bit 0 CMP1: Compare 1 interrupt flag This bit is set by hardware when the timer x counter matches the value programmed in the compare 1 register.
Page 935 RM0440 High-resolution timer (HRTIM) Bit 7 CPT1C: Capture 1 interrupt flag clear Writing 1 to this bit clears the CPT1 flag in HRTIM_TIMxISR register Bit 6 UPDC: Update interrupt flag clear Writing 1 to this bit clears the UPD flag in HRTIM_TIMxISR register Bit 5 Reserved, must be kept at reset value.
Page 936 High-resolution timer (HRTIM) RM0440 Bit 31 Reserved, must be kept at reset value. Bit 30 DLYPRTDE: Delayed protection DMA request enable This bit is set and cleared by software to enable/disable DMA requests on delayed protection. 0: Delayed protection DMA request disabled 1: Delayed protection DMA request enabled Bit 29 RSTDE: Reset/roll-over DMA request enable This bit is set and cleared by software to enable/disable DMA requests on timer x counter reset or...
Page 937 RM0440 High-resolution timer (HRTIM) Bit 16 CMP1DE: Compare 1 DMA request enable This bit is set and cleared by software to enable/disable the compare 1 DMA requests. 0: Compare 1 DMA request disabled 1: Compare 1 DMA request enabled Bit 15 Reserved, must be kept at reset value. Bit 14 DLYPRTIE: Delayed protection interrupt enable This bit is set and cleared by software to enable/disable interrupts on delayed protection.
Page 938 High-resolution timer (HRTIM) RM0440 Bit 2 CMP3IE: Compare 3 interrupt enable Refer to CMP1IE description Bit 1 CMP2IE: Compare 2 interrupt enable Refer to CMP1IE description Bit 0 CMP1IE: Compare 1 interrupt enable This bit is set and cleared by software to enable/disable the compare 1 interrupts. 0: Compare 1 interrupt disabled 1: Compare 1 interrupt enabled 938/2083...
Page 939 RM0440 High-resolution timer (HRTIM) 26.5.16 HRTIM timer x counter register (HRTIM_CNTxR) (x = A to F) Address offset: Block A: 0x090 Address offset: Block B: 0x110 Address offset: Block C: 0x190 Address offset: Block D: 0x210 Address offset: Block E: 0x290 Address offset: Block F: 0x310 Reset value: 0x0000 0000 Res.
Page 940 High-resolution timer (HRTIM) RM0440 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PERx[15:0]: Timer x period value This register holds timer x period value. This register holds either the content of the preload register or the content of the active register if preload is disabled.
Page 941 RM0440 High-resolution timer (HRTIM) 26.5.18 HRTIM timer x repetition register (HRTIM_REPxR) (x = A to F) Address offset: Block A: 0x098 Address offset: Block B: 0x118 Address offset: Block C: 0x198 Address offset: Block D: 0x218 Address offset: Block E: 0x298 Address offset: Block F: 0x318 Reset value: 0x0000 0000 Res.
Page 942 High-resolution timer (HRTIM) RM0440 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP1x[15:0]: Timer x compare 1 value This register holds the compare 1 value. This register holds either the content of the preload register or the content of the active register if preload is disabled.
Page 943 RM0440 High-resolution timer (HRTIM) 26.5.20 HRTIM timer x compare 1 compound register (HRTIM_CMP1CxR) (x = A to F) Address offset: Block A: 0x0A0 Address offset: Block B: 0x120 Address offset: Block C: 0x1A0 Address offset: Block D: 0x220 Address offset: Block E: 0x2A0 Address offset: Block F: 0x320 Reset value: 0x0000 0000 Res.
Page 944 High-resolution timer (HRTIM) RM0440 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP2x[15:0]: Timer x compare 2 value This register holds the compare 2 value. This register holds either the content of the preload register or the content of the active register if preload is disabled.
Page 945 RM0440 High-resolution timer (HRTIM) 26.5.22 HRTIM timer x compare 3 register (HRTIM_CMP3xR) (x = A to F) Address offset: Block A: 0x0A8 Address offset: Block B: 0x128 Address offset: Block C: 0x1A8 Address offset: Block D: 0x228 Address offset: Block E: 0x2A8 Address offset: Block F: 0x328 Reset value: 0x0000 0000 Res.
Page 946 High-resolution timer (HRTIM) RM0440 26.5.23 HRTIM timer x compare 4 register (HRTIM_CMP4xR) (x = A to F) Address offset: Block A: 0x0AC Address offset: Block B: 0x12C Address offset: Block C: 0x1AC Address offset: Block D: 0x22C Address offset: Block E: 0x2AC Address offset: Block F: 0x32C Reset value: 0x0000 0000 Res.
Page 947 RM0440 High-resolution timer (HRTIM) 26.5.24 HRTIM timer x capture 1 register (HRTIM_CPT1xR) (x = A to F) Address offset: Block A: 0x0B0 Address offset: Block B: 0x130 Address offset: Block C: 0x1B0 Address offset: Block D: 0x230 Address offset: Block E: 0x2B0 Address offset: Block F: 0x330 Reset value: 0x0000 0000 Res.
Page 948 High-resolution timer (HRTIM) RM0440 26.5.25 HRTIM timer x capture 2 register (HRTIM_CPT2xR) (x = A to F) Address offset: Block A: 0x0B4 Address offset: Block B: 0x134 Address offset: Block C: 0x1B4 Address offset: Block D: 0x234 Address offset: Block E: 0x2B4 Address offset: Block F: 0x334 Reset value: 0x0000 0000 Res.
Page 949 RM0440 High-resolution timer (HRTIM) 26.5.26 HRTIM timer x deadtime register (HRTIM_DTxR) (x = A to F) Address offset: Block A: 0x0B8 Address offset: Block B: 0x138 Address offset: Block C: 0x1B8 Address offset: Block D: 0x238 Address offset: Block E: 0x2B8 Address offset: Block F: 0x338 Reset value: 0x0000 0000 DTFLK...
Page 950 High-resolution timer (HRTIM) RM0440 Bit 14 DTRSLKx: Deadtime rising sign lock This write-once bit prevents the sign of deadtime to be modified, if enabled. 0: Deadtime rising sign is writable 1: Deadtime rising sign is read-only Note: This bit is not preloaded. Bit 13 Reserved, must be kept at reset value.
Page 951 RM0440 High-resolution timer (HRTIM) 26.5.27 HRTIM timer x output 1 set register (HRTIM_SETx1R) (x = A to F) Address offset: Block A: 0x0BC Address offset: Block B: 0x13C Address offset: Block C: 0x1BC Address offset: Block D: 0x23C Address offset: Block E: 0x2BC Address offset: Block F: 0x33C Reset value: 0x0000 0000 UPDAT...
Page 952 High-resolution timer (HRTIM) RM0440 Bit 19 TIMEVNT8: Timer event 8 Refer to TIMEVNT1 description. Bit 18 TIMEVNT7: Timer event 7 Refer to TIMEVNT1 description. Bit 17 TIMEVNT6: Timer event 6 Refer to TIMEVNT1 description. Bit 16 TIMEVNT5: Timer event 5 Refer to TIMEVNT1 description.
Page 953 RM0440 High-resolution timer (HRTIM) Bit 2 PER: Timer x period Timer A period event forces the output to its active state. Note: In up/down mode (UDM bit set to 1), the counter period event is defined as per the OUTROM[1:0] bit setting. Bit 1 RESYNC: Timer A resynchronization Timer A reset event coming solely from software or SYNC input forces the output to its active state.
Page 954 High-resolution timer (HRTIM) RM0440 26.5.28 HRTIM timer x output 2 reset register (HRTIM_RSTx1R) (x = A to F) Address offset: Block A: 0x0C0 Address offset: Block B: 0x140 Address offset: Block C: 0x1C0 Address offset: Block D: 0x240 Address offset: Block E: 0x2C0 Address offset: Block F: 0x340 Reset value: 0x0000 0000 UPDAT...
Page 955 RM0440 High-resolution timer (HRTIM) 26.5.30 HRTIM timer x output 2 reset register (HRTIM_RSTx2R) (x = A to F) Address offset: Block A: 0x0C8 Address offset: Block B: 0x148 Address offset: Block C: 0x1C8 Address offset: Block D: 0x248 Address offset: Block E: 0x2C8 Address offset: Block F: 0x348 Reset value: 0x0000 0000 UPDAT...
Page 956 High-resolution timer (HRTIM) RM0440 26.5.31 HRTIM timer x external event filtering register 1 (HRTIM_EEFxR1) (x = A to F) Address offset: Block A: 0x0CC Address offset: Block B: 0x14C Address offset: Block C: 0x1CC Address offset: Block D: 0x24C Address offset: Block E: 0x2CC Address offset: Block F: 0x34C Reset value: 0x0000 0000 EE5LT...
Page 957 RM0440 High-resolution timer (HRTIM) Bit 5 Reserved, must be kept at reset value. Bits 4:1 EE1FLTR[3:0]: External event 1 filter 0000: No filtering 0001: Blanking from counter reset/roll-over to compare 1 0010: Blanking from counter reset/roll-over to compare 2 in up-counting mode (UDM bit reset) In up-down counting mode (UDM bit set): blanking from compare 1 to compare 2, only during the up-counting phase.
Page 958 High-resolution timer (HRTIM) RM0440 26.5.32 HRTIM timer x external event filtering register 2 (HRTIM_EEFxR2) (x = A to F) Address offset: Block A: 0x0D0 Address offset: Block B: 0x150 Address offset: Block C: 0x1D0 Address offset: Block D: 0x250 Address offset: Block E: 0x2D0 Address offset: Block F: 0x350 Reset value: 0x0000 0000 EE10LT...
Page 959 RM0440 High-resolution timer (HRTIM) Bit 5 Reserved, must be kept at reset value. Bits 4:1 EE6FLTR[3:0]: External event 6 filter Refer to EE1FLTR[3:0] description. Bit 0 EE6LTCH: External event 6 latch Refer to EE1LTCH description. 26.5.33 HRTIM timer A reset register (HRTIM_RSTAR) Address offset: 0x0D4 Reset value: 0x0000 0000 TIMF...
Page 960 High-resolution timer (HRTIM) RM0440 Bit 19 TIMBCMP1: Timer B compare 1 The timer A counter is reset upon timer B compare 1 event. Bit 18 EXTEVNT10: External event The timer A counter is reset upon external event 10. Bit 17 EXTEVNT9: External event 9 The timer A counter is reset upon external event 9.
Page 961 RM0440 High-resolution timer (HRTIM) 26.5.34 HRTIM timer B reset register (HRTIM_RSTBR) Address offset: 0x154 Reset value: 0x0000 0000 TIMF TIME TIME TIME TIMD TIMD TIMD TIMC TIMC TIMC TIMA TIMA TIMA EVNT CMP2 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4...
Page 962 High-resolution timer (HRTIM) RM0440 Bit 16 EXTEVNT8: External event 8 The timer B counter is reset upon external event 8. Bit 15 EXTEVNT7: External event 7 The timer B counter is reset upon external event 7. Bit 14 EXTEVNT6: External event 6 The timer B counter is reset upon external event 6.
Page 963 RM0440 High-resolution timer (HRTIM) 26.5.35 HRTIM timer C reset register (HRTIM_RSTCR) Address offset: 0x2D4 Reset value: 0x0000 0000 TIMF TIME TIME TIME TIMD TIMD TIMD TIMB TIMB TIMB TIMA TIMA TIMA EVNT CMP2 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4...
Page 964 High-resolution timer (HRTIM) RM0440 Bit 16 EXTEVNT8: External event 8 The timer C counter is reset upon external event 8. Bit 15 EXTEVNT7: External event 7 The timer C counter is reset upon external event 7. Bit 14 EXTEVNT6: External event 6 The timer C counter is reset upon external event 6.
Page 965 RM0440 High-resolution timer (HRTIM) 26.5.36 HRTIM timer D reset register (HRTIM_RSTDR) Address offset: 0x254 Reset value: 0x0000 0000 TIMF TIME TIME TIME TIMC TIMC TIMC TIMB TIMB TIMB TIMA TIMA TIMA EVNT CMP2 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4...
Page 966 High-resolution timer (HRTIM) RM0440 Bit 16 EXTEVNT8: External event 8 The timer D counter is reset upon external event 8. Bit 15 EXTEVNT7: External event 7 The timer D counter is reset upon external event 7. Bit 14 EXTEVNT6: External event 6 The timer D counter is reset upon external event 6.
Page 967 RM0440 High-resolution timer (HRTIM) 26.5.37 HRTIM timer E reset register (HRTIM_RSTER) Address offset: 0x2D4 Reset value: 0x0000 0000 TIMF TIMD TIMD TIMD TIMC TIMC TIMC TIMB TIMB TIMB TIMA TIMA TIMA EVNT CMP2 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4...
Page 968 High-resolution timer (HRTIM) RM0440 Bit 16 EXTEVNT8: External event 8 The timer E counter is reset upon external event 8. Bit 15 EXTEVNT7: External event 7 The timer E counter is reset upon external event 7. Bit 14 EXTEVNT6: External event 6 The timer E counter is reset upon external event 6.
Page 969 RM0440 High-resolution timer (HRTIM) 26.5.38 HRTIM timer F reset register (HRTIM_RSTFR) Address offset: 0x354 Reset value: 0x0000 0000 TIME TIMD TIMD TIMD TIMC TIMC TIMC TIMB TIMB TIMB TIMA TIMA TIMA EVNT CMP2 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4 CMP2 CMP1 CMP4...
Page 970 High-resolution timer (HRTIM) RM0440 Bit 16 EXTEVNT8: External event 8 The timer F counter is reset upon external event 8. Bit 15 EXTEVNT7: External event 7 The timer F counter is reset upon external event 7. Bit 14 EXTEVNT6: External event 6 The timer F counter is reset upon external event 6.
Page 971 RM0440 High-resolution timer (HRTIM) 26.5.39 HRTIM timer x chopper register (HRTIM_CHPxR) (x = A to F) Address offset: Block A: 0x0D8 Address offset: Block B: 0x158 Address offset: Block C: 0x1D8 Address offset: Block D: 0x258 Address offset: Block E: 0x2D8 Address offset: Block F: 0x358 Reset value: 0x0000 0000 Res.
Page 972 High-resolution timer (HRTIM) RM0440 26.5.40 HRTIM timer A capture 1 control register (HRTIM_CPT1ACR) Address offset: 0x0DC Reset value: 0x0000 0000 CMP2 CMP1 CMP2 CMP1 CMP2 CMP1 CMP2 CMP1 EXEV1 EXEV9 EXEV8 EXEV7 EXEV6 EXEV5 EXEV4 EXEV3 EXEV2 EXEV1 CMP2 CMP1 0CPT Bits 31:0 Refer to HRTIM_CPT2xCR bit description 26.5.41...
Page 973 RM0440 High-resolution timer (HRTIM) 26.5.43 HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) Address offset: 0x25C Reset value: 0x0000 0000 CMP2 CMP1 CMP2 CMP1 CMP2 CMP1 CMP2 CMP1 EXEV1 EXEV9 EXEV8 EXEV7 EXEV6 EXEV5 EXEV4 EXEV3 EXEV2 EXEV1 CMP2 CMP1 0CPT Bits 31:0 Refer to HRTIM_CPT2xCR bit description 26.5.44...
Page 974 High-resolution timer (HRTIM) RM0440 26.5.46 HRTIM timer x capture 2 control register (HRTIM_CPT2xCR) (x = A to F) Address offset: Block A: 0x0E0 Address offset: Block B: 0x160 Address offset: Block C: 0x1E0 Address offset: Block D: 0x260 Address offset: Block E: 0x2E0 Address offset: Block F: 0x360 Reset value: 0x0000 0000 CMP2...
Page 975 RM0440 High-resolution timer (HRTIM) Bit 31 In HRTIM_CPT2ACR, HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2DCR, HRTIM_CPT2FCR: TECMP2: Timer E compare 2 Refer to TACMP2 description. In HRTIM_CPT2ECR: TFCMP2: Timer F compare 2 Refer to TACMP2 description. Bit 30 In HRTIM_CPT2ACR, HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2DCR, HRTIM_CPT2FCR: TECMP1: Timer E compare 1 Refer to TACMP1 description.
Page 976 High-resolution timer (HRTIM) RM0440 Bit 26 In HRTIM_CPT2ACR, HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TDCMP1:Timer D compare 1 Refer to TACMP1 description. In HRTIM_CPT2DCR: TFCMP1: Timer F compare 1 Refer to TACMP1 description. Bit 25 In HRTIM_CPT2ACR, HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TD1RST: Timer D output 1 reset Refer to TA1RST description.
Page 977 RM0440 High-resolution timer (HRTIM) Bit 20 In HRTIM_CPT2ACR, HRTIM_CPT2BCR, HRTIM_CPT2DCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TC1SET: Timer C output 1 set Refer to TA1SET description. In HRTIM_CPT2CCR: TF1SET: Timer F output 1 set Refer to TA1SET description. Bit 19 In HRTIM_CPT2ACR, HRTIM_CPT2CCR, HRTIM_CPT2DCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TBCMP2: Timer B compare 2 Refer to TACMP2 description.
Page 978 High-resolution timer (HRTIM) RM0440 Bit 15 In HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2DCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TACMP2: Timer A compare 2 0: No action 1: Timer A compare 2 triggers capture 2 In HRTIM_CPT2ACR: TFCMP2: Timer E compare 2 Refer to TACMP2 description. Bit 14 In HRTIM_CPT2BCR, HRTIM_CPT2CCR, HRTIM_CPT2DCR, HRTIM_CPT2ECR, HRTIM_CPT2FCR: TACMP1: Timer A compare 1...
Page 979 RM0440 High-resolution timer (HRTIM) Bit 6 EXEV5CPT: External event 5 capture Refer to EXEV1CPT description. Bit 5 EXEV4CPT: External event 4 capture Refer to EXEV1CPT description. Bit 4 EXEV3CPT: External event 3 capture Refer to EXEV1CPT description. Bit 3 EXEV2CPT: External event 2 capture Refer to EXEV1CPT description.
Page 980 High-resolution timer (HRTIM) RM0440 26.5.47 HRTIM timer x output register (HRTIM_OUTxR) (x = A to F) Address offset: Block A: 0x0E4 Address offset: Block B: 0x164 Address offset: Block C: 0x1E4 Address offset: Block D: 0x264 Address offset: Block E: 0x2E4 Address offset: Block F: 0x364 Reset value: 0x0000 0000 IDLEM...
Page 981 RM0440 High-resolution timer (HRTIM) Bit 18 IDLEM2: Output 2 idle mode This bit selects the output 2 idle mode. 0: No action: the output is not affected by the burst mode operation. 1: The output is in idle state when requested by the burst mode controller. Note: This bit is preloaded and is changed during run-time, but must not be changed while the burst mode is active.
Page 982 High-resolution timer (HRTIM) RM0440 Bit 8 DTEN: Deadtime enable This bit enables the deadtime insertion on output 1 and output 2. 0: Output 1 and output 2 signals are independent. 1: Deadtime is inserted between output 1 and output 2 (reference signal is output 1 signal generator) Note: This parameter cannot be changed once the timer is operating (TxEN bit set) or if its outputs are enabled and set/reset by another timer.
Page 983 RM0440 High-resolution timer (HRTIM) 26.5.48 HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F) Address offset: Block A: 0x0E8 Address offset: Block B: 0x168 Address offset: Block C: 0x1E8 Address offset: Block D: 0x268 Address offset: Block E: 0x2E8 Address offset: Block F: 0x368 Reset value: 0x0000 0000 Res.
Page 984 High-resolution timer (HRTIM) RM0440 26.5.49 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F) Address offset: Block A: 0x0EC Address offset: Block B: 0x16C Address offset: Block C: 0x1EC Address offset: Block D: 0x26C Address offset: Block E: 0x2EC Address offset: Block F: 0x36C Reset value: 0x0000 0000 Res.
Page 985 RM0440 High-resolution timer (HRTIM) Bits 15:14 FEROM[1:0]: Fault and event roll-over mode This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the Roll- over event used by the fault and event counters. 00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value 01: Event generated when the counter is equal to 0 10: Event generated when the counter is equal to HRTIM_PERxR 11: Reserved...
Page 986 High-resolution timer (HRTIM) RM0440 Bit 4 UDM: Up-Down mode This bit defines if the counter is operating in up or up-down counting mode. 0: The counter is operating in up-counting mode 1: The counter is operating in up-down counting mode Note: This bit cannot be changed once the timer is operating (TxEN bit set).
Page 987 RM0440 High-resolution timer (HRTIM) 26.5.50 HRTIM timer x external event filtering register 3 (HRTIM_TIMxEEFR3) (x = A to F) Address offset: Block A: 0x0F0 Address offset: Block B: 0x170 Address offset: Block C: 0x1F0 Address offset: Block D: 0x270 Address offset: Block E: 0x2F0 Address offset: Block F: 0x370 Reset value: 0x0000 0000 Res.
Page 988 High-resolution timer (HRTIM) RM0440 26.5.51 HRTIM control register 1 (HRTIM_CR1) Address offset: 0x380 Reset value: 0x0000 0000 Res. Res. Res. Res. AD4USRC[2:0] AD3USRC[2:0] AD2USRC[2:0] AD1USRC[2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. MUDIS UDIS UDIS UDIS UDIS UDIS UDIS Bits 31:28 Reserved, must be kept at reset value.
Page 989 RM0440 High-resolution timer (HRTIM) Bit 2 TBUDIS: Timer B update disable Refer to TAUDIS description. Bit 1 TAUDIS: Timer A update disable This bit is set and cleared by software to enable/disable an update event generation temporarily on timer A. 0: Update enabled.
Page 990 High-resolution timer (HRTIM) RM0440 26.5.52 HRTIM control register 2 (HRTIM_CR2) Address offset: 0x384 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWPF SWPE SWPD SWPC SWPB SWPA Res. TFRST TERST TDRST TCRST TBRST TARST MRST Res.
Page 991 RM0440 High-resolution timer (HRTIM) Bit 10 TBRST: Timer B counter software reset Refer to TARST description. Bit 9 TARST: Timer A counter software reset Setting this bit resets the timer A counter. The bit is automatically reset by hardware. Bit 8 MRST: Master counter software reset Setting this bit resets the master timer counter.
Page 992 High-resolution timer (HRTIM) RM0440 Bits 31:18 Reserved, must be kept at reset value. Bit 17 BMPER: Burst mode period interrupt flag This bit is set by hardware when a single-shot burst mode operation is completed or at the end of a burst mode period in continuous mode.
Page 993 RM0440 High-resolution timer (HRTIM) 26.5.54 HRTIM interrupt clear register (HRTIM_ICR) Address offset: 0x38C Reset value: 0x0000 0000 BMPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDYC SYSFL Res. Res. Res. Res. Res. Res. Res.
Page 994 High-resolution timer (HRTIM) RM0440 26.5.55 HRTIM interrupt enable register (HRTIM_IER) Address offset: 0x390 Reset value: 0x0000 0000 BMPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDYIE FLT6 SYSFL Res. Res. Res. Res. Res. Res.
Page 995 RM0440 High-resolution timer (HRTIM) 26.5.56 HRTIM output enable register (HRTIM_OENR) Address offset: 0x394 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TF2O TF1O TE2O TE1O TD2O TD1O TC2O TC1O TB2O TB1O...
Page 996 High-resolution timer (HRTIM) RM0440 26.5.57 HRTIM output disable register (HRTIM_ODISR) Address offset: 0x398 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ODIS ODIS ODIS ODIS ODIS ODIS...
Page 997 RM0440 High-resolution timer (HRTIM) 26.5.58 HRTIM output disable status register (HRTIM_ODSR) Address offset: 0x39C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:12 Reserved, must be kept at reset value. Bit 11 TF2ODS: Timer F output 2 disable status Refer to TA1ODS description.
Page 998 High-resolution timer (HRTIM) RM0440 26.5.59 HRTIM burst mode control register (HRTIM_BMCR) Address offset: 0x3A0 Reset value: 0x0000 0000 BMSTA Res. Res. Res. Res. Res. Res. Res. Res. TFBM TEBM TDBM TCBM TBBM TABM MTBM rc_w0 BMPR Res. Res. Res. Res. Res.
Page 999 RM0440 High-resolution timer (HRTIM) Bits 9:6 BMPRSC[3:0]: Burst mode prescaler Defines the prescaling ratio of the f clock for the burst mode controller. This bitfield cannot be HRTIM changed while the burst mode is enabled. 0000: Clock not divided 0001: Division by 2 0010: Division by 4 0011: Division by 8 0100: Division by 16...
Page 1000 High-resolution timer (HRTIM) RM0440 26.5.60 HRTIM burst mode trigger register (HRTIM_BMTRGR) Address offset: 0x3A4 Reset value: 0x0000 0000 OCHP TDEEV TAEEV TECMP TECMP TDCM TCCM EEV8 EEV7 TEREP TDREP TDRST TCREP CMP1 TBCMP TBCMP TACMP TACMP MSTC MSTC MSTC MSTC MSTRE MSTRS TCRST...

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