Analog-to-digital converters (ADC)
Figure 138. Interleaved mode on 1 channel in single conversion mode: dual ADC
MASTER ADC
SLAVE ADC
If DISCEN=1, each "n" simultaneous conversions ("n" is defined by DISCNUM) of the
regular sequence require a regular trigger event to occur.
In this mode, injected conversions are supported. When injection is done (either on master
or on slave), both the master and the slave regular conversions are aborted and the
sequence is restarted from the master (see
ADC1 (master)
ADC2 (slave)
Legend:
Sampling
Alternate trigger mode
This mode is selected by programming bits DUAL[4:0] = 01001.
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of the master ADC.
This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0.
Injected discontinuous mode disabled (JDISCEN=0 for both ADC)
634/3748
0.5 ADCCLK
cycle
CH1
Trigger
4 ADCCLK
cycles
Sampling
Conversion
Figure 139. Interleaved conversion with injection
Injected trigger
CH1
CH1
CH2
CH2
read
CDR
Conversion
RM0440 Rev 1
mode
0.5 ADCCLK
CH1
End of conversion on
4 ADCCLK
master and slave ADC
Figure 139
below).
Resume (always on master)
CH11
CH1
CH2
read
conversions
CDR
aborted
cycle
CH1
CH1
End of conversion on
cycles
master and slave ADC
CH1
CH1
CH2
CH2
read
CDR
RM0440
MSv31031V3
CH1
CH0
read
CDR
MS34460V1
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