Table 50. Interconnect 1 - ST STM32G4 Series Reference Manual

RM0440
Table 49. STM32G4 Series peripherals interconnect matrix
Source
2 2
2 2 2
3 3
COMP6 3 4 4
8 4
5 5 5
9 5
2 2
2 2
3 2 3
COMP7 4 4
8 3 4
5 5
9 5
SYST ERR 18 - - - -
1. Numbers inside table link to corresponding interconnect number detailed in
2. The "-" symbol in grayed cells means no interconnect.
10.3 Interconnection details
10.3.1 From timer (TIMx, HRTIM) to timer (TIMx)
Timer input
trigger signal
TIM1
timx_itr0 -
timx_itr1 tim2_trgo
timx_itr2 tim3_trgo
timx_itr3 tim4_trgo
timx_itr4 tim5_trgo
timx_itr5 tim8_trgo
timx_itr6 tim15_trgo
timx_itr7 tim16_oc
timx_itr8 tim17_oc
timx_itr9 tim20_trgo
hrtim_out_
timx_itr10
scout2
The HRTIM burst operation can be triggered by on chip event coming from other general
purpose timer.
2 2
3 3
3 3 3 10
- - 5 5 -
8 8 8 11
8 8
9 9
2 3 2
3 4 3 3 3 10
- - -
8 5 8 8 8 11
9 8 9
- - 18 18 18 18 18 - 18

Table 50. Interconnect 1

Timer input trigger source assignement
TIM2 TIM3
tim1_trgo tim1_trgo
- tim2_trgo
tim3_trgo -
tim4_trgo tim4_trgo
tim5_trgo tim5_trgo
tim8_trgo tim8_trgo
tim15_trgo tim15_trgo
tim16_oc tim16_oc
tim17_oc tim17_oc
tim20_trgo tim20_trgo
hrtim_out_ hrtim_out_
scout2 scout2
Destination
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
Section 10.3: Interconnection
TIM4 TIM5
tim1_trgo tim1_trgo
tim2_trgo tim2_trgo
tim3_trgo tim3_trgo
- tim4_trgo
tim5_trgo -
tim8_trgo tim8_trgo
tim15_trgo tim15_trgo
tim16_oc tim16_oc
tim17_oc tim17_oc
tim20_trgo tim20_trgo
hrtim_out_ hrtim_out_
scout2 scout2
RM0440 Rev 1
Peripherals interconnect matrix
(1) (2)
(continued)
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
details.
TIM8 TIM15
tim1_trgo tim1_trgo
tim2_trgo tim2_trgo
tim3_trgo tim3_trgo
tim4_trgo tim4_trgo
tim5_trgo tim5_trgo
- tim8_trgo
tim15_trgo -
tim16_oc tim16_oc
tim17_oc tim17_oc
tim20_trgo tim20_trgo
hrtim_out_ hrtim_out_
scout2 scout2
- - - - -
- - - - -
- - - - -
TIM20
tim1_trgo
tim2_trgo
tim3_trgo
tim4_trgo
tim5_trgo
tim8_trgo
tim15_trgo
tim16_oc
tim17_oc
-
hrtim_out_
scout2
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