Hsi48 Clock; Pll; Lse Clock - ST STM32G4 Series Reference Manual

RM0440
The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
6.2.3

HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used
directly for USB and for random number generator (RNG).
The internal 48 MHz RC oscillator is mainly dedicated to provide a high precision clock to
the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. The CRS
can use the LSE or an external signal to automatically and quickly adjust the oscillator
frequency on-fly. It is disabled as soon as the system enters Stop or Standby mode. When
the CRS is not used, the HSI48 RC oscillator runs on its default frequency which is subject
to manufacturing process variations.
The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the
HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not
released until this bit is set by hardware.
The HSI48 can be switched on and off using the HSI48ON bit in the Clock recovery RC
register (RCC_CRRCR).
6.2.4

PLL

The internal PLL can be used to multiply the HSI16 or HSE output clock frequency. The PLL
input frequency must be between 4 and 16 MHz. The selected clock source is divided by a
programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input
range. Refer to
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in
configuration register
An interrupt can be generated when the PLL is ready, if enabled in the
enable register
The PLL output frequency must not exceed 170 MHz.
The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at
any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is
used as system clock.
6.2.5

LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
Section 6.2.9: Clock security system (CSS) on page
Figure 14: Clock treeand
(RCC_PLLCFGR).
(RCC_CIER).
RM0440 Rev 1
Reset and clock control (RCC)
PLL configuration register
Clock control register
239.
(RCC_PLLCFGR).
(RCC_CR).
PLL
Clock interrupt
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