ST STM32G4 Series Reference Manual page 728

Digital-to-analog converter (DAC)
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and Hold mode).
Hold time= (THOLD[9:0]) x LSI/LSE clock period
Note: This register can be modified only when EN2=0.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and Hold mode)
Hold time= (THOLD[9:0]) x LSI/LSE clock period
Note: This register can be modified only when EN1=0.
Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.
21.7.20 DAC sample and hold refresh time register (DAC_SHRR)
Address offset: 0x4C
Reset value: 0x0001 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and Hold mode)
Refresh time= (TREFRESH[7:0]) x LSI/LSE clock period
Note: This register can be modified only when EN2=0.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 TREFRESH1[7:0]: DAC channel1 refresh time (only valid in Sample and Hold mode)
Refresh time= (TREFRESH[7:0]) x LSI/LSE clock period
Note: This register can be modified only when EN1=0.
Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.
728/2083
These bits are available only on dual-channel DACs. Refer to
implementation.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits are available only on dual-channel DACs. Refer to
implementation.
24 23 22
Res.
rw rw
8 7 6
Res.
rw rw
RM0440 Rev 1
Section 21.3: DAC
21 20 19 18
TREFRESH2[7:0]
rw rw rw rw
5 4 3 2
TREFRESH1[7:0]
rw rw rw rw
Section 21.3: DAC
RM0440
17 16
rw rw
1 0
rw rw