Table 343. Usart Interrupt Requests - ST STM32G4 Series Reference Manual

RM0440
Determining the maximum USART baud rate that allows to correctly wake up
the microcontroller from low-power mode
The maximum baud rate allowing to correctly wake up the microcontroller from low-power
mode depends on the wakeup time parameter (refer to the device datasheet) and on the
USART receiver tolerance (see
deviation).
Let us take the example of OVER8 = 0, M bits = '01', ONEBIT = 0 and BRR [3:0] = 0000.
In these conditions, according to
[3:0] = 0000, the USART receiver tolerance equals 3.41%.
DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance
D
WUmax
T
bit Min
where t
If we consider the ideal case where DTRA, DQUANT, DREC and DTCL parameters are at
0%, the maximum value of DWU is 3.41%. In reality, we need to consider at least the
usart_ker_ck inaccuracy.
For example, if HSI16 is used as usart_ker_ck, and the HSI16 inaccuracy is of 1%, then we
obtain:
t
WUUSART
device datasheet).
D
WUmax
T
bit min
As a result, the maximum baud rate allowing to wakeup correctly from low-power mode
is: 1/11.32 µs = 88.36 Kbaud.
36.6 USART interrupts
During USART communications, an interrupt (usart_it) can be generated by different events.
The USART block can also generate a wakeup interrupt (usart_wkup).
Refer to
Interrupt event
Transmit data register empty
Transmit FIFO Not Full
Transmit FIFO Empty
Universal synchronous/asynchronous receiver transmitter (USART/UART)
= t / (11 x T
WUUSART
= = t / (11 x D
WUUSART
is the wakeup time from low-power mode.
WUUSART
= 3 µs (values provided only as examples; for correct values, refer to the
= 3.41% - 1% = 2.41%
= 3 µs/ (11 x 2.41%) = 11.32 µs.
Table 343 for a detailed description of all USART interrupt requests.

Table 343. USART interrupt requests

Enable
Event
Control
flag
bit
TXE TXEIE
TXFNF TXFNFIE
TXFE TXFEIE
Section 36.5.8: Tolerance of the USART receiver to clock
Table 340: Tolerance of the USART receiver when BRR
)
bit Min
)
WUmax
Interrupt clear method
TXE cleared when a data is
written in TDR
TXFNF cleared when TXFIFO
is full.
TXFE cleared when the
TXFIFO contains at least one
data or by setting TXFRQ bit.
RM0440 Rev 1
Interrupt activated
usart_it usart_wkup
YES NO
YES NO
YES YES
1601/2083
1692