ST STM32G4 Series Reference Manual page 216
Advanced arm-based 32-bit mcus
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- Reference manual (2126 pages) ,
- Programming manual (262 pages) ,
- Application note (56 pages)
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Power control (PWR)
Bit 2 WP3: Wakeup pin WKUP3 polarity
Bit 1 WP2: Wakeup pin WKUP2 polarity
Bit 0 WP1: Wakeup pin WKUP1 polarity
5.4.5
Power status register 1 ( PWR_SR1 )
Address offset: 0x10
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register.
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
WUFI
Res.
Res.
Res.
r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Wakeup flag internal
Bits 14:9 Reserved, must be kept at reset value.
Bit 8 SBF: Standby flag
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUF5: Wakeup flag 5
Bit 3 WUF4: Wakeup flag 4
216/2083
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
This bit is set by hardware when the device enters the Standby mode and is cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter the Standby mode
1: The device entered the Standby mode
This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by
writing '1' in the CWUF5 bit of the PWR_SCR register.
This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by
writing '1' in the CWUF4 bit of the PWR_SCR register.
24
23
22
Res.
Res.
Res.
8
7
6
SBF
Res.
Res.
r
RM0440 Rev 1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
WUF5
WUF4
WUF3
r
r
r
RM0440
17
16
Res.
Res.
1
0
WUF2
WUF1
r
r
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