(Discen=1, Jdiscen=1) - ST STM32G4 Series Reference Manual

RM0440
Figure 119. AUTODLY=1, regular HW conversions interrupted by injected conversions
Regular
trigger
ADC
RDY CH1
state
regular
EOC
EOS
ADC_DR read access
ADC_DR
Injected
trigger
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

(DISCEN=1, JDISCEN=1)

Ignored
DLY RDY CH2 DLY
regular
DLY (CH1)
DLY (CH2)
D1
by h/w
Not ignored
(occurs during injected sequence)
RDY CH5 RDY CH6
injected injected
D2
Ignored
RM0440 Rev 1
Analog-to-digital converters (ADC)
CH3 DLY RDY CH1
regular
regular
DLY (CH3)
D3
Ignored
DLY (inj)
D5
D6
Indicative timings
DLY RDYCH2
regular
DLY (CH1)
D1
MS31022V1
615/3748
683