ST STM32G4 Series Reference Manual page 665

RM0440
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:0 L[3:0]: Regular channel sequence length
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
20.6.12 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SQ7[3:0]
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 23 Reserved, must be kept at reset value.
These bits are written by software with the channel number (0..18) assigned as the 3rd in the
regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 2nd in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 1st in the
regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
no regular conversion is ongoing).
28 27 26 25
SQ9[4:0]
rw rw rw rw
12 11 10 9
Res.
rw rw rw
These bits are written by software with the channel number (0..18) assigned as the 9th in the
regular conversion sequence.
no regular conversion is ongoing).
24 23 22
Res.
rw rw
8 7 6
SQ6[4:0] Res.
rw rw rw
RM0440 Rev 1
Analog-to-digital converters (ADC)
21 20 19 18
SQ8[4:0]
rw rw rw rw
5 4 3 2
SQ5[4:0]
rw rw rw
17 16
Res. SQ7[4]
rw
1 0
rw rw
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