Figure 449. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 450. Capture/Compare Channel 1 Main Circuit - ST STM32G4 Series Reference Manual

RM0440

Figure 449. Capture/compare channel (example: channel 1 input stage)

TIMx_TISEL
TI1SEL[3:0]
tim_ti1_in0
TIM_CH1
tim_ti1_in[1..15]
f
DTS
The output stage generates an intermediate waveform which is then used for reference:
tim_ocxref (active high). The polarity acts at the end of the chain.
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
Filter
downcounter
tim_ti1f Edge
detector
ICF[3:0]
TIMx_CCMR1

Figure 450. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
Counter
RM0440 Rev 1
General-purpose timers (TIM15/TIM16/TIM17)
tim_ti1f_ed
tim_ti1f_rising
0
TI1FP1
tim_ti1f_falling
1
tim_ti2fp1
CC1P/CC1NP
tim_trc
TIMx_CCER
(from slave mode
controller)
tim_ti2f_rising
0
(from channel 2)
tim_ti2f_falling
1
(from channel 2)
8
write_in_progress
compare_transfer
Comparator
To the slave mode controller
01
tim_ec1
Divider
10
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
write CCR1H
S
write CCR1L
R
Output
CC1S[1]
mode
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
tim_ic1f
CC1E
TIMx_CCER
MSv62322V1
OC1PE
TIMx_CCMR1
MS31089V4
1315/2083
1399