ST STM32G4 Series Reference Manual page 213

Advanced arm-based 32-bit mcus

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Power control register 2 (PWR_CR2)

Address offset: 0x04

Reset value: 0x0000 0000. This register is reset when exiting Standby mode.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 PVMEN2: Peripheral voltage monitoring 4 enable:

Bit 6 PVMEN1: Peripheral voltage monitoring 3 enable:

Bits 5:4 Reserved, must be kept at reset value.

Bits 3:1 PLS[2:0]: Power voltage detector level selection.

Note: These bits are write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2

Bit 0 PVDE: Power voltage detector enable

Note: This bit is write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2

Power control register 3 (PWR_CR3)

Address offset: 0x08

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with

the PWRRST bit in the RCC_APB1RSTR1 register.

Access: Additional APB cycles are needed to access this register vs. a standard APB

access (3 for a write and 2 for a read).

monitoring vs. 1.8 V threshold) disable.

monitoring vs. 1.8 V threshold) enable.

monitoring vs. 1.62V threshold) disable.

monitoring vs. 1.62V threshold) enable.

These bits select the PVD falling threshold:

111: External input analog voltage PVD_IN (compared internally to V

0: Power voltage detector disable.

1: Power voltage detector enable.

RM0440 Rev 1

Power control (PWR)

vs. DAC 1MSPS /DAC 15MSPS min

vs. ADC/COMP min voltage 1.62V

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