Ccm Sram Read Protection; Ccm Sram Erase - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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1. Available on Category 3 devices only.

The write protection can be enabled in

mechanism, which means by writing '1' on a bit it sets up the write protection for that page of

SRAM and it can be removed/cleared by a system reset only.

CCM SRAM read protection

The CCMSRAM is protected with the Read protection (RDP). Refer to

protection (RDP)

The CCMSRAM can be erased with a system reset using the option bit CCMSRAM_RST in

the user option byte (refer to

The CCM SRAM erase can also be requested by software by setting the bit CCMSR in the

Section 9.2.7: SYSCFG CCM SRAM control and status register

Table 4. CCM SRAM organization (continued)

in the SYSCFG block. This is a register with write '1' once

for more details.

Section 3.4.1: Option bytes

Start address

Section 9.2.9: SYSCFG CCM SRAM write protection

RM0440 Rev 1

Section 3.5.1: Read

description).

(SYSCFG_SCSR).

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