Table 292. Output Control Bits For Complementary Tim_Ocx And Tim_Ocxn Channels With Break; Feature (Tim15) - ST STM32G4 Series Reference Manual

RM0440

Table 292. Output control bits for complementary tim_ocx and tim_ocxn channels with break

Control bits
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit tim_ocx output state
1 X
0
0
1
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
Note: The state of the external I/O pins connected to the complementary tim_ocx and tim_ocxn
channels depends on the tim_ocx and tim_ocxn channel state and AFIO registers.
X 0 0
0 0 1
0 1 0
X 1 1
1 0 1
1 1 0
X X
0 0
0 1
X
1 0
1 1
General-purpose timers (TIM15/TIM16/TIM17)

feature (TIM15)

Output Disabled (not driven by the timer: Hi-Z)
tim_ocx=0
tim_ocxn=0
Output Disabled (not driven
by the timer: Hi-Z)
tim_ocx=0
tim_ocxref + Polarity
tim_ocx=tim_ocxref XOR
CCxP
tim_ocxref + Polarity +
dead-time
Off-State (output enabled
with inactive state)
tim_ocx=CCxP
tim_ocxref + Polarity
tim_ocx=tim_ocxref xor
CCxP
Output disabled (not driven by the timer anymore). The
output state is defined by the GPIO controller and can be
High, Low or Hi-Z.
Off-State (output enabled with inactive state)
Asynchronously: tim_ocx=CCxP, tim_ocxn=CCxNP
Then if the clock is present: tim_ocx=OISx and
tim_ocxn=OISxN after a dead-time, assuming that OISx and
OISxN do not correspond to tim_ocx and tim_ocxn both in
active state
RM0440 Rev 1
(1)
Output states
tim_ocxn output state
tim_ocxref + Polarity
tim_ocxn=tim_ocxref XOR
CCxNP
Output Disabled (not driven by
the timer: Hi-Z)
tim_ocxn=0
Complementary to tim_ocxref
(not OCREF) + Polarity + dead-
time
tim_ocxref + Polarity
tim_ocxn=tim_ocxref XOR
CCxNP
Off-State (output enabled with
inactive state)
tim_ocxn=CCxNP
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