ST STM32G4 Series Reference Manual page 717

RM0440
Bit 15:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
Note: This bit is cleared by hardware (one dac_hclk clock cycle later) once the DAC_DHR2
Bit 0 SWTRIG1: DAC channel1 software trigger
Note: This bit is cleared by hardware (one dac_hclk clock cycle later) once the DAC_DHR1
21.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC1DHRB[11:0]: DAC channel1 12-bit right-aligned data B
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
register value has been loaded into the DAC_DOR2 register.
This bit is available only on dual-channel DACs. Refer to
implementation.
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
register value has been loaded into the DAC_DOR1 register.
27 26 25
rw rw rw
11 10 9
rw rw rw
These bits are written by software. They specify 12-bit data for DAC channel1 when the
DAC operates in Double data mode.
These bits are written by software. They specify 12-bit data for DAC channel1.
24 23 22
DACC1DHRB[11:0]
rw rw rw
8 7 6
DACC1DHR[11:0]
rw rw rw
RM0440 Rev 1
Digital-to-analog converter (DAC)
Section 21.3: DAC
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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