Timer Clock; Watchdog Clock - ST STM32G4 Series Reference Manual

RM0440
6.2.13

Timer clock

The timer clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
6.2.14

Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
6.2.15 Clock-out capability
•
MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of eight clock signals can be selected as the MCO clock.
–
–
–
–
–
–
–
The selection is controlled by the MCOSEL[3:0] bits of the
(RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the
Clock configuration register
• LSCO
Another output (LSCO) allows a low speed clock to be output onto the external LSCO
pin:
–
–
This output remains available in Stop (Stop 0 and Stop 1) and Standby modes. The
selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the
domain control register
The MCO clock output requires the corresponding alternate function selected on the MCO
pin, the LSCO pin should be left in default POR state.
6.2.16 Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17
It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM5, TIM15, TIM16 or TIM17 channel 1 input capture, as represented on
Figure 17,
LSI
LSE
SYSCLK
HSI16
HSI48
HSE
PLLCLK
LSI
LSE
(RCC_BDCR).
Figure 18 and Figure
(RCC_CFGR).
19.
RM0440 Rev 1
Reset and clock control (RCC)
Clock configuration register
Figure 16
RTC
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