Figure 430. Gating Tim_Slv With Tim_Oc1Ref Of Tim_Mstr - ST STM32G4 Series Reference Manual

RM0440
1. Configure TIM_mstr in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIM_mstr_CR2 register, a rising edge
is output on tim_trgo each time an update event is generated.
2. To connect the tim_trgo output of TIM_mstr to TIM_slv, TIM_slv must be configured in
slave mode using ITR2 as internal trigger. This is selected through the TS bits in the
TIM_slv_SMCR register (writing TS=00010).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIM_slv_SMCR register). This causes TIM_slv to be clocked by the rising edge of
the periodic TIM_mstr trigger signal (which correspond to the TIM_mstr counter
overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If tim_ocx is selected on TIM_mstr as the trigger output (MMS=1xx), its rising edge is used
to clock the counter of TIM_slv.
Using one timer to enable another timer
In this example, we control the enable of TIM_slv with the output compare 1 of TIM_mstr.
Refer to
tim_oc1ref of TIM_mstr is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to tim_ker_ck (f
1. Configure TIM_mstr master mode to send its Output Compare 1 Reference
(tim_oc1ref) signal as trigger output (MMS=100 in the TIM_mstr_CR2 register).
2. Configure the TIM_mstr tim_oc1ref waveform (TIM_mstr_CCMR1 register).
3. Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the
TIM_slv_SMCR register).
4. Configure TIM_slv in gated mode (SMS=101 in TIM_slv_SMCR register).
5. Enable TIM_slv by writing '1 in the CEN bit (TIM_slv_CR1 register).
6. Start TIM_mstr by writing '1 in the CEN bit (TIM_mstr_CR1 register).
Note: The slave timer counter clock is not synchronized with the master timer counter clock, this
mode only affects the TIM_slv counter enable signal.
TIM_mst_oc1ref
tim_mstr_CNT
tim_slv_CNT
tim_slv TIF bit
Figure 429 for connections. TIM_slv counts on the divided internal clock only when

Figure 430. Gating TIM_slv with tim_oc1ref of TIM_mstr

tim_ker_ck
FC
3045
Write TIF = 0
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
= f
tim_cnt_ck tim_ker_ck
FD FE
3046 3047
RM0440 Rev 1
/3).
FF 00 01
3048
MSv62376V1
1253/2083
1297