ST STM32G4 Series Reference Manual page 938

Advanced arm-based 32-bit mcus

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High-resolution timer (HRTIM)

Bit 2 CMP3IE: Compare 3 interrupt enable

Refer to CMP1IE description

Bit 1 CMP2IE: Compare 2 interrupt enable

Refer to CMP1IE description

Bit 0 CMP1IE: Compare 1 interrupt enable

This bit is set and cleared by software to enable/disable the compare 1 interrupts.

0: Compare 1 interrupt disabled

1: Compare 1 interrupt enabled

RM0440 Rev 1

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