Figure 564. Reception Using Dma; Figure 565. Hardware Flow Control Between 2 Lpuarts - ST STM32G4 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
TX line
RXNE flag
DMA request
LPUART_RDR
DMA reads
LPUART_RDR
DMA TCIF flag
(transfer complete)
Software configures
the DMA to receive 3
datablocks and
enables the LPUART
Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not
empty (i.e. RXFNE = 1).
Error flagging and interrupt generation in multibuffer communication
If any error occurs during a transaction In multibuffer communication mode, the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in
case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt
enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the
current byte if any of these errors occur.
37.3.13 RS232 Hardware flow control and RS485 Driver Enable
It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The
1660/2083

Figure 564. Reception using DMA

Frame 1
Set by hardware
cleared by DMA read
F 1
DMA reads F1
from
LPUART_RDR
Figure 551 shows how to connect 2 devices in this mode:

Figure 565. Hardware flow control between 2 LPUARTs

LPUART 1
TX
TX circuit
CTS
RX
RX circuit
RTS
RM0440 Rev 1
Frame 2
F2
DMA reads F2 DMA reads F3
from
LPUART_RDR LPUART_RDR
RX
RTS
TX
CTS
RM0440
Frame 3
F3
Cleared by
Set by hardware
software
DMA transfer is
complete
from
(TCIF=1 in
DMA_ISR)
MSv31891V3
LPUART 2
RX circuit
TX circuit
MSv31892V2