ST STM32G4 Series Reference Manual page 866

High-resolution timer (HRTIM)
When the power converter set-point has to be adjusted by software, TAUDIS, TDUDIS and
TEUDIS bits of the HRTIM_CR register must be set prior to write accessing the registers to
update the values (for instance the compare values). From this time on, any hardware
update request is ignored and the preload registers can be accessed without any risk to
have them transferred into the active registers. Once the software processing is over,
TAUDIS, TDUDIS and TEUDIS bits can be reset: the transfer from preload to active
registers is done as soon as the timer A repetition event occurs.
26.3.12 PWM mode with "greater than" comparison
A specific no-latency update mode is available for PWM signals generated with the CMP1
and CMP3 registers. It allows to have a new duty cycle value applied as soon as possible
within the PWM cycle, without having to wait the completion of the current PWM period. This
reduces the overall delay time in software control loops. As shown on
eventually allows to have:
–
–
The output signal is left unchanged when the new compare value and current compare
value are both below the counter.
This feature is only available for CMP1 or CMP3 RESET events, and is enabled using the
GTCMP1 and GTCMP3 enable bits in the HRTIM_TIMxCR2 register.
The preload mechanism is inactive for a compare register when the corresponding
GTCMPx bit is set, whatever the PREEN bit value. This mode is intended to have the new
compare value taken into account as soon as possible after a new value write, without
waiting for the preload to active register transfer.
These bits are defining the compare 1 and compare 3 operating modes as following
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–
The "greater than" compare mode causes the crossbar to act differently depending on
comparison result. Let's consider the CMP1 event is doing an output RESET. When the new
compare value is written, two cases are considered
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–
The "greater than" compare mode is supported for both SET and RESET actions.
The "greater than" compare mode must only be used for the following configuration:
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an early turn-off of the output if the new compare value is below the current
counter value and the current compare value is above the counter, at the time the
new value is written.
an early turn-on of the output, re-enabling the output if the new compare value is
above the counter value and the current compare value is above the counter, at
the time the new value is written.
GTCMPx = 0: the compare x event is generated when the counter is equal to the
compare value (compare match mode). If the compare value is changed on-the-
fly, the compare event may not be generated.
GTCMPx = 1: the compare x event is generated when the counter is greater than
the compare value. If the compare value is changed on-the-fly, the new compare
value is compared with the current counter value and an output SET or RESET
can be generated.
If the new compare value is below the counter value, the RESET event is issued
and can eventually cause an early turn-OFF
If the new compare value is above the counter value, a SET event is generated so
as to re-arm the output value before it is actually RESET when the counter
exceeds the counter value (early turn-ON).
RM0440 Rev 1
RM0440
Figure 230 below, this