ST STM32G4 Series Reference Manual page 663

RM0440
Bits 15: Reserved, must be kept at reset value.
Bits 14:12 AWDFILT: Analog watchdog filtering parameter
This bit is set and cleared by software.
000: No filtering
001: two consecutive detection generates an AWDx flag or an interrupt
...
111: Eight consecutive detection generates an AWDx flag or an interrupt
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
20.6.9 ADC watchdog threshold register 2 (ADC_TR2)
Address offset: 0x24
Reset value: 0x00FF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 2.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 2.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Section 20.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Section 20.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
Section 20.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
24 23 22
Res.
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8 7 6
Res.
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RM0440 Rev 1
Analog-to-digital converters (ADC)
21 20 19 18
HT2[7:0]
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5 4 3 2
LT2[7:0]
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17 16
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1 0
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