ST STM32G4 Series Reference Manual page 263

Advanced arm-based 32-bit mcus

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APB1 peripheral reset register 2 (RCC_APB1RSTR2)

Address offset: 0x3C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 UCPD1RST: UCPD1 reset

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 I2C4RST: I2C4 reset

Bit 0 LPUART1RST: Low-power UART 1 reset

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x40

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Set and cleared by software.

0: No effect

1: Reset UCPD1

Set and cleared by software

0: No effect

1: Reset I2C4

Set and cleared by software.

0: No effect

1: Reset LPUART1

RM0440 Rev 1

Reset and clock control (RCC)

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