Table 277. Output Control Bit For Standard Tim_Ocx Channels - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bit 9 CC3P: Capture/Compare 3 output Polarity.
Bit 8 CC3E: Capture/Compare 3 output enable.
Bit 7 CC2NP: Capture/Compare 2 output Polarity.
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
Bit 4 CC2E: Capture/Compare 2 output enable.
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
Bit 0 CC1E: Capture/Compare 1 output enable.
CCxE bit
0
1
1278/2083
Refer to CC1P description
Refer to CC1E description
Refer to CC1NP description
refer to CC1P description
Refer to CC1E description
CC1 channel configured as output: CC1NP must be kept cleared in this case.
CC1 channel configured as input: This bit is used in conjunction with CC1P to define
tim_ti1fp1/tim_ti2fp1 polarity. refer to CC1P description.
CC1 channel configured as output:
0: tim_oc1 active high
1: tim_oc1 active low
CC1 channel configured as input: CC1NP/CC1P bits select tim_ti1fp1 and tim_ti2fp1
polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to tim_tixfp1 rising edge (capture, trigger in reset, external clock or trigger
mode), tim_tixfp1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to tim_tixfp1 falling edge (capture, trigger in reset, external clock or trigger
mode), tim_tixfp1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both tim_tixfp1 rising and falling edges (capture, trigger in reset,
external clock or trigger mode), tim_tixfp1 is not inverted (trigger in gated mode). This
configuration must not be used for encoder mode.
CC1 channel configured as output:
0: Off - tim_oc1 is not active
1: On - tim_oc1 signal is output on the corresponding output pin
CC1 channel configured as input: This bit determines if a capture of the counter value can
actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 277. Output control bit for standard tim_ocx channels

tim_ocx output state
Output disabled (tim_ocx = 0, I/O controlled by GPIO controller)
Output enabled (tim_ocx = tim_ocxref + Polarity)
RM0440 Rev 1
RM0440