ST STM32G4 Series Reference Manual page 558

Quad-SPI interface (QUADSPI)
19.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
Address offset: 0x0024
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 MASK[31:0]: Status mask
19.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
Address offset: 0x0028
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 MATCH[31:0]: Status match
558/2083
27 26 25 24
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11 10 9 8
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Mask to be applied to the status bytes received in polling mode.
For bit n:
0: Bit n of the data received in automatic polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic polling mode is unmasked and its value is
considered in the matching logic
This field can be written only when BUSY = 0.
27 26 25 24
MATCH[31:16]
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11 10 9 8
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Value to be compared with the masked status register to get a match.
This field can be written only when BUSY = 0.
RM0440 Rev 1
23 22 21
MASK[31:16]
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7 6 5
MASK[15:0]
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23 22 21
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7 6 5
MATCH[15:0]
rw rw rw
20 19 18 17
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4 3 2 1
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20 19 18 17
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4 3 2 1
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RM0440
16
rw
0
rw
16
rw
0
rw