ST STM32G4 Series Reference Manual page 275

Advanced arm-based 32-bit mcus
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RM0440
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes
Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 FMACSMEN: FMACSM clock enable.
Bit 3 CORDICSMEN: CORDICSM clock enable.
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during Sleep and Stop modes.
Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes
Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
Set and cleared by software.
0: CRC clocks disabled by the clock gating
1: CRC clocks enabled by the clock gating
Set and cleared by software.
0: SRAM1 interface clocks disabled by the clock gating
1: SRAM1 interface clocks enabled by the clock gating
Set and cleared by software.
0: Flash memory interface clocks disabled by the clock gating
modes
1: Flash memory interface clocks enabled by the clock gating
modes
Set and cleared by software.
0: FMACSM clocks disabled by the clock gating
1: FMACSM clocks enabled by the clock gating
Set and cleared by software.
0: CORDICSM clocks disabled.
1: CORDICSM clocks enabled.
Set and cleared by software.
0: DMAMUX1 clocks disabled by the clock gating
1: DMAMUX1 clocks enabled by the clock gating
Set and cleared by software during Sleep mode.
0: DMA2 clocks disabled by the clock gating
1: DMA2 clocks enabled by the clock gating
Set and cleared by software.
0: DMA1 clocks disabled by the clock gating
1: DMA1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
during Sleep and Stop modes
(1)
(1)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0440 Rev 1
Reset and clock control (RCC)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop
(1)
during Sleep and Stop
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
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