ST STM32G4 Series Reference Manual page 7

RM0440
6.2.15
6.2.16
6.2.17
6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11
6.4.12
6.4.13
6.4.14
6.4.15
6.4.16
6.4.17
6.4.18
6.4.19
6.4.20
6.4.21
6.4.22
6.4.23
6.4.24
6.4.25
6.4.26
6.4.27
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17 . 241
Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 244
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 247
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 248
PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 250
Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 253
Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 254
Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 255
AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 256
AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 258
AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 260
APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 260
APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 263
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 263
AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 265
AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 266
AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 268
APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 269
APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 271
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 273
AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Peripherals independent clock configuration register (RCC_CCIPR) . 283
RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 286
RM0440 Rev 1
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