ST STM32G4 Series Reference Manual page 999

RM0440
Bits 9:6 BMPRSC[3:0]: Burst mode prescaler
Defines the prescaling ratio of the f
changed while the burst mode is enabled.
0000: Clock not divided
0001: Division by 2
0010: Division by 4
0011: Division by 8
0100: Division by 16
0101: Division by 32
0110: Division by 64
0111: Division by 128
1000: Division by 256
1001: Division by 512
1010: Division by 1024
1011: Division by 2048
1100: Division by 4096
1101: Division by 8192
1110: Division by 16384
1111: Division by 32768
Bits 5:2 BMCLK[3:0]: Burst mode clock source
This bitfield defines the clock source for the burst mode counter. It cannot be changed while the burst
mode is enabled (refer to
0000: Master timer counter reset/roll-over
0001: Timer A counter reset/roll-over
0010: Timer B counter reset/roll-over
0011: Timer C counter reset/roll-over
0100: Timer D counter reset/roll-over
0101: Timer E counter reset/roll-over
0110: On-chip event 1 (hrtim_bm_ck1), acting as a burst mode counter clock
0111: On-chip event 2 (hrtim_bm_ck2) acting as a burst mode counter clock
1000: On-chip event 3 (hrtim_bm_ck3) acting as a burst mode counter clock
1001: On-chip event 4 (hrtim_bm_ck4) acting as a burst mode counter clock
1010: Prescaled f
1011: Timer F counter reset/roll-over
Others: Reserved
Bit 1 BMOM: Burst mode operating mode
This bit defines if the burst mode is entered once or if it is continuously operating.
0: Single-shot mode
1: Continuous operation
Bit 0 BME: Burst mode enable
This bit starts the burst mode controller which becomes ready to receive the start trigger.
Writing this bit to 0 causes a burst mode early termination.
0: Burst mode disabled
1: Burst mode enabled
clock for the burst mode controller. This bitfield cannot be
HRTIM
Table 203 for on-chip events 1..4 connections details).
clock (as per BMPRSC[3:0] setting)
HRTIM
RM0440 Rev 1
High-resolution timer (HRTIM)
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