Figure 379. Control Circuit In External Clock Mode 2; Figure 380. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32G4 Series Reference Manual

RM0440
tim_ker_ck
tim_cnt_ck
tim_psc_ck
Counter register
28.4.6 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding tim_tix input to generate a filtered signal
tim_tixf. Then, an edge detector with polarity selection generates a signal (tim_tixfpy) which
can be used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 380. Capture/compare channel (example: channel 1 input stage)

TIMx_TISEL
TI1SEL[3:0]
tim_ti1_in0
TIM_CH1
tim_ti1_in[1..15]
f
DTS

Figure 379. Control circuit in external clock mode 2

CEN
tim_etr_in
tim_etrp
tim_etrf
Filter
downcounter
tim_ti1f Edge
detector
ICF[3:0]
TIMx_CCMR1
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
34
tim_ti1f_ed
tim_ti1f_rising
0
TI1FP1
tim_ti1f_falling
1
tim_ti2fp1
CC1P/CC1NP
tim_trc
TIMx_CCER
(from slave mode
controller)
tim_ti2f_rising
0
(from channel 2)
tim_ti2f_falling
1
(from channel 2)
RM0440 Rev 1
35
To the slave mode controller
01
tim_ec1
Divider
10
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
CC1E
TIMx_CCER
TIMx_CCMR1
1207/2083
36
MSv62321V1
tim_ic1f
MSv62322V1
1297