ST STM32G4 Series Reference Manual page 660

Analog-to-digital converters (ADC)
Bit 9 TROVS: Triggered Regular Oversampling
This bit is set and cleared by software to enable triggered oversampling
0: All oversampled conversions for a channel are done consecutively following a trigger
1: Each oversampled conversion for a channel needs a new trigger
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 8:5 OVSS[3:0]: Oversampling shift
This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling
result.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 4:2 OVSR[2:0]: Oversampling ratio
This bitfield is set and cleared by software to define the oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 1 JOVSE: Injected Oversampling Enable
This bit is set and cleared by software to enable injected oversampling.
0: Injected Oversampling disabled
1: Injected Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)
Bit 0 ROVSE: Regular Oversampling Enable
This bit is set and cleared by software to enable regular oversampling.
0: Regular Oversampling disabled
1: Regular Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)
660/3748 RM0440 Rev 1
RM0440