ST STM32G4 Series Reference Manual page 992

Advanced arm-based 32-bit mcus

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High-resolution timer (HRTIM)

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 BMPER: Burst mode period interrupt flag

This bit is set by hardware when a single-shot burst mode operation is completed or at the end of a

burst mode period in continuous mode. It is cleared by software writing it at 1.

0: No burst mode period interrupt occurred

1: Burst mode period interrupt occurred

Bit 16 DLLRDY: DLL Ready Interrupt Flag

This bit is set by hardware when the DLL calibration is completed. It is cleared by software writing it

0: No DLL calibration ready interrupt occurred

1: DLL calibration ready interrupt occurred

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 FLT6: Fault 6 interrupt flag

Refer to FLT1 description.

Bit 5 SYSFLT: System fault interrupt flag

Refer to FLT1 description.

Bit 4 FLT5: Fault 5 interrupt flag

Refer to FLT1 description.

Bit 3 FLT4: Fault 4 interrupt flag

Refer to FLT1 description.

Bit 2 FLT3: Fault 3 interrupt flag

Refer to FLT1 description.

Bit 1 FLT2: Fault 2 interrupt flag

Refer to FLT1 description.

Bit 0 FLT1: Fault 1 interrupt flag

This bit is set by hardware when fault 1 event occurs. It is cleared by software writing it at 1.

0: No fault 1 interrupt occurred

1: Fault 1 interrupt occurred

RM0440 Rev 1

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