Table 207. Period And Compare Registers Min And Max Values; Table 208. Timer Operating Modes - ST STM32G4 Series Reference Manual

RM0440
CKPSC[2:0] value
1. The value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse. See
Null duty cycle exception case
Note: A compare value greater than the period register value does not generate a compare match
event.
Counter operating mode
Timer A..F operate in continuous (free-running) mode or in single-shot manner where
counting is started by a reset event, using the CONT bit in the HRTIM_TIMxCR control
register. An additional RETRIG bit allows you to select whether the single-shot operation is
retriggerable or non-retriggerable. Details of operation are summarized on
Figure 182
CONT RETRIG Operating mode
0 0
Non-retriggerable
0 1
Retriggerable
1 X Continuous mode
The TxEN bit can be cleared at any time to disable the timer and stop the counting.

Table 207. Period and compare registers min and max values

0
1
2
3
4
≥ 5
for details.
and Figure 183.

Table 208. Timer operating modes

Setting the TxEN bit enables the timer but does not start the counter.
A first reset event starts the counting and any subsequent reset is ignored
Single-shot
until the counter reaches the PER value.
The PER event is then generated and the counter is stopped.
A reset event re-starts the counting operation from 0x0000.
Setting the TxEN bit enables the timer but does not start the counter.
A reset event starts the counting if the counter is stopped, otherwise it
Single-shot
clears the counter. When the counter reaches the PER value, the PER
event is generated and the counter is stopped.
A reset event re-starts the counting operation from 0x0000.
Setting the TxEN bit enables the timer and starts the counter
simultaneously.
When the counter reaches the PER value, it rolls-over to 0x0000 and
resumes counting.
The counter can be reset at any time.
(1)
Min
0x0060
0x0030
0x0018
0x000C
0x0006
0x0003
Start / stop conditions
Clocking and event generation
RM0440 Rev 1
High-resolution timer (HRTIM)
Max
0xFFDF
0xFFEF
0xFFF7
0xFFFB
0xFFFD
0xFFFD
Section :
Table 208 and on
813/2083
1040