Figure 247. Counter Behavior In Synchronized Start Mode - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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High-resolution timer (HRTIM)

Internal reset

Internal reset

ADC triggers

The ADCs can be triggered by the master and the 6 timing units.

10 independent triggers are available for both the regular and the injected sequencers of the

ADCs. The external events can be used as triggers. They are taken right after the

conditioning defined in the HRTIM_EECRx registers, and are not depending on the EEFxR1

and EEFxR2 register settings.

Up to 32 events can be combined (ORed) for ADC triggers 1 to 4, in HRTIM_ADC1R to

HRTIM_ADC4R registers, as shown on

the same source set. A multiple triggering is possible within a single switching period by

selecting several sources simultaneously. A typical use case is for a non-overlapping

multiphase converter, where all phases can be sampled in a row using a single ADC trigger

presents how the synchronized start is done in single-shot mode.

Figure 247. Counter behavior in synchronized start mode

SYNCSTRT, Single-shot mode, non-retriggerable

Counter initialized by software

SYNCSTRT, Single-shot mode, retriggerable

248. The ADC triggers 1/3 and 2/4 are using

RM0440 Rev 1

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