Figure 613. Audio Block Clock Generator Overview - ST STM32G4 Series Reference Manual

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Serial audio interface (SAI)

Generation of the bit clock (SCK_x)

The clock generator provides the bit clock (SCK_x) when the audio block is defined as

Master. The frame synchronization (FS_x) is also derived from the signals provided by the

clock generator.

In Slave mode, the value of NODIV and OSR fields are ignored, and the SCK_x clock is not

The bit clock strobing edge of SCK_x can be configured through the CKSTR fields, which is

functional both in master and slave mode.

The NODIV bit must be used to force the ratio between the master clock (MCLK_x) and the

frame synchronization (FS_x) frequency to 256 or 512.

If NODIV is set to 0, the frequency ratio between the frame synchronization and the

master clock is fixed to 512 or 256, according to OSR value, but the frame length must

be a power of 2. More details are given hereafter.

If NODIV is set to 1, the application can adjust the frequency of the bit clock (SCK_x)

via MCKDIV. In addition there is no restriction on the frame length value as long as the

frame length is bigger or equal to 8 (i.e. FRL[7:0] > 6). The frame synchronization

frequency depends on MCKDIV and frame length (FRL[7:0]). In that case, the

frequency of the MCLK_x is equal to the SCK_x.

The NODIV, MCKEN, SAIEN, OVR, CKSTR and MCKDIV[5:0] bits belong to the SAI_xCR1

illustrates the architecture of the audio block clock generator.

Figure 613. Audio block clock generator overview

SAI clock generator x

Clock divider

Audio Block x

[0]: FRL+1 must be a power of 2 when NOMCK = 0

RM0440 Rev 1

SAIEN for block x

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