Table 124. Fmc_Btrx Bit Fields; Table 125. Fmc_Bwtrx Bit Fields - ST STM32G4 Series Reference Manual

Flexible memory controller (FMC)
Bit number
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don't care.
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Table 123. FMC_BCRx bit fields (continued)
Bit name
MTYP 0x2 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1

Table 124. FMC_BTRx bit fields

Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD accesses and DATAHLD+1 HCLK cycles for write accesses when
Extended mode is disabled).
ACCMOD 0x1 if Extended mode is set
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the access first phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.

Table 125. FMC_BWTRx bit fields

Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x1 if Extended mode is set
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the access first phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
RM0440 Rev 1
Value to set
Value to set
Value to set
RM0440