ST STM32G4 Series Reference Manual page 988

High-resolution timer (HRTIM)
26.5.51 HRTIM control register 1 (HRTIM_CR1)
Address offset: 0x380
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:25 AD4USRC[2:0]: ADC trigger 4 update source
Refer to AD1USRC[2:0] description.
Bits 24:22 AD3USRC[2:0]: ADC trigger 3 update source
Refer to AD1USRC[2:0] description.
Bits 21:19 AD2USRC[2:0]: ADC trigger 2 update source
Refer to AD1USRC[2:0] description.
Bits 18:16 AD1USRC[2:0]: ADC trigger 1 update source
These bits define the source which triggers the update of the HRTIM_ADC1R register (transfer from
preload to active register). It only defines the source timer. The precise condition is defined within the
timer itself, in HRTIM_MCR or HRTIM_TIMxCR.
000: Master timer
001: Timer A
010: Timer B
011: Timer C
100: Timer D
101: Timer E
110: Timer F
111: Reserved
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TFUDIS: Timer F update disable
Refer to TAUDIS description.
Bit 5 TEUDIS: Timer E update disable
Refer to TAUDIS description
Bit 4 TDUDIS: Timer D update disable
Refer to TAUDIS description.
Bit 3 TCUDIS: Timer C update disable
Refer to TAUDIS description.
988/2083
28 27 26 25
AD4USRC[2:0]
rw rw rw
12 11 10 9
Res. Res. Res.
24 23 22
AD3USRC[2:0]
rw rw rw
8 7 6
TF
Res. Res.
UDIS UDIS
rw
RM0440 Rev 1
21 20 19 18
AD2USRC[2:0]
rw rw rw rw
5 4 3 2
TE TD TC TB
UDIS UDIS UDIS
rw rw rw rw
RM0440
17 16
AD1USRC[2:0]
rw rw
1 0
TA
MUDIS
UDIS
rw rw