Preloaded) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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Basic timers (TIM6/TIM7)

Figure 484. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

Auto-reload preload

Auto-reload shadow

Write a new value in TIMx_ARR

Dithering mode

The time base effective resolution can be increased by enabling the dithering mode, using

the DITHEN bit in the TIMx_CR1 register. This affects the way the TIMx_ARR is behaving,

and is useful for adjusting the average counter period when the timer is used as a trigger

(typically for a DAC).

The operating principle is to have the actual ARR value slightly changed (adding or not one

timer clock period) over 16 consecutive counting periods, with predefined patterns. This

allows a 16-fold resolution increase, considering the average counting period.

below presents the dithering principle applied to 4 consecutive counting

preloaded)

RM0440 Rev 1

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