Figure 249. Adc Triggers - ST STM32G4 Series Reference Manual

High-resolution timer (HRTIM)
Master Cmp1,2,3,4 + PER
External Events 1..5
TimerA Cmp3,4 + PER + RST
TimerB Cmp3,4 + PER + RST
TimerC Cmp3,4 + PER
TimerD Cmp3,4 + PER
TimerE Cmp3,4 + PER
TimerF Cmp2,3,4 + PER + RST
AD5USRC
Master update
Timer A update
Timer B update
Timer C update
Timer D update
Timer E update
Timer F update
HRTIM_ADC1R to HRTIM_ADC4R and HRTIM_ADCER registers are preloaded and can
be updated synchronously with the timer they are related to. The update sources are
defined with ADxUSRC[2:0] bits in the HRTIM_CR1 and HRTIM_ADCUR registers.
For instance, if ADC trigger 1 outputs timer A CMP2 events (HRTIM_ADC1R = 0x0000
0400), HRTIM_ADC1R is typically updated simultaneously with timer A (AD1USRC[2:0] =
001).
When the preload is disabled (PREEN bit reset) in the source timer, the HRTIM_ADCxR
registers are not preloaded either: a write access results in an immediate update of the
trigger source.
ADC post-scaler
A post-scaling unit allows to reduce the ADC trigger rate as shown in
Each ADC trigger rate can be individually adjusted using the ADCxPSC[4:0] bits in the
HRTIM_ADCxPS1 and HRTIM_ADCxPS2 registers.
In the center-aligned mode, the ADC trigger rate is also dependent on ADROM[1:0] bitfield,
programmed in the source timer, as shown in
for any event that can trigger the ADC: reset, roll-over (period) and compare event:
•
ADROM[1:0] = 00: event generated both during up and down-counting phases
•
ADROM[1:0] = 01: event generated during down-counting phases
•
ADROM[1:0] = 10: event generated during up-counting phases
896/2083
hrtim_adc hrtim_adc hrtim_adc
_trg5 _trg7 _trg9
5
5
5
ADC ADC ADC
Trigger 5 Trigger 7 Trigger 9
5
1 Source 1 source 1 Source
4
only only only
4
4
Trigger 5 Trigger 7 Trigger 9
4
Update Update Update
AD7USRC AD9USRC
Sources in bold are available only on Trigger 5,7,9 or trigger 6,8,10

Figure 249. ADC triggers

Master Cmp1,2,3,4 + PER
External Events 6..10
TimerA Cmp2,4 + PER
TimerB Cmp2,4 + PER
TimerC Cmp2,4 + PER + RST
TimerD Cmp2,4 + PER + RST
TimerE Cmp2,3,4 + RST
TimerF Cmp2,3,4 + PER
Figure 251. The ADROM[1:0] bitfield is coding
RM0440 Rev 1
hrtim_adc hrtim_adc
_trg6 _trg8
5
5
4
ADC ADC
Trigger 6 Trigger 8
4
1 Source 1 source
5
only only
5
4
Trigger 6 Trigger 8
4
Update Update
AD6USRC AD8USRC AD10USRC
Figure 250
RM0440
hrtim_adc
_trg10
ADC
Trigger 10
1 Source
only
Trigger 10
Update
MSv48357V2
below.