ST STM32G4 Series Reference Manual page 921

RM0440
26.5.4 HRTIM master timer DMA interrupt enable register (HRTIM_MDIER)
Address offset: 0x00C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 MUPDDE: Master update DMA request enable
This bit is set and cleared by software to enable/disable the master update DMA requests.
0: Master update DMA request disabled
1: Master update DMA request enabled
Bit 21 SYNCDE: Sync input DMA request enable
This bit is set and cleared by software to enable/disable the sync input DMA requests.
0: Sync input DMA request disabled
1: Sync input DMA request enabled
Bit 20 MREPDE: Master repetition DMA request enable
This bit is set and cleared by software to enable/disable the master timer repetition DMA requests.
0: Repetition DMA request disabled
1: Repetition DMA request enabled
Bit 19 MCMP4DE: Master compare 4 DMA request enable
Refer to MCMP1DE description
Bit 18 MCMP3DE: Master compare 3 DMA request enable
Refer to MCMP1DE description
Bit 17 MCMP2DE: Master compare 2 DMA request enable
Refer to MCMP1DE description
Bit 16 MCMP1DE: Master compare 1 DMA request enable
This bit is set and cleared by software to enable/disable the master timer compare 1 DMA requests.
0: Compare 1 DMA request disabled
1: Compare 1 DMA request enabled
Bits 15:6 Reserved, must be kept at reset value.
Bit 6 MUPDIE: Master update interrupt enable
This bit is set and cleared by software to enable/disable the master timer registers update interrupts
0: Master update interrupts disabled
1: Master update interrupts enabled
Bit 5 SYNCIE: Sync input interrupt enable
This bit is set and cleared by software to enable/disable the sync input interrupts
0: Sync input interrupts disabled
1: Sync input interrupts enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
MUPD SYNCD
Res. Res.
DE
rw
8 7 6
MUPDI SYNCI
Res. Res.
E
rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
MREP MCMP MCMP
E DE 4DE 3DE
rw rw rw rw
5 4 3 2
MREPI MCMP MCMP
E E 4IE 3IE
rw rw rw rw
17 16
MCMP MCMP
2DE 1DE
rw rw
1 0
MCMP MCMP
2IE 1IE
rw rw
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