ST STM32G4 Series Reference Manual page 24

Contents
26.5.41 HRTIM timer B capture 1 control register (HRTIM_CPT1BCR) . . . . . . 972
26.5.42 HRTIM timer C capture 1 control register (HRTIM_CPT1CCR) . . . . . 972
26.5.43 HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) . . . . . 973
26.5.44 HRTIM timer E capture 1 control register (HRTIM_CPT1ECR) . . . . . . 973
26.5.45 HRTIM timer F capture 1 control register (HRTIM_CPT1FCR) . . . . . . 973
26.5.46 HRTIM timer x capture 2 control register (HRTIM_CPT2xCR)
26.5.47 HRTIM timer x output register (HRTIM_OUTxR) (x = A to F) . . . . . . . 980
26.5.48 HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F) . . . . . . . . . . 983
26.5.49 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F) . . . . 984
26.5.50 HRTIM timer x external event filtering register 3 (HRTIM_TIMxEEFR3)
26.5.51 HRTIM control register 1 (HRTIM_CR1) . . . . . . . . . . . . . . . . . . . . . . . 988
26.5.52 HRTIM control register 2 (HRTIM_CR2) . . . . . . . . . . . . . . . . . . . . . . . 990
26.5.53 HRTIM interrupt status register (HRTIM_ISR) . . . . . . . . . . . . . . . . . . . 991
26.5.54 HRTIM interrupt clear register (HRTIM_ICR) . . . . . . . . . . . . . . . . . . . . 993
26.5.55 HRTIM interrupt enable register (HRTIM_IER) . . . . . . . . . . . . . . . . . . 994
26.5.56 HRTIM output enable register (HRTIM_OENR) . . . . . . . . . . . . . . . . . . 995
26.5.57 HRTIM output disable register (HRTIM_ODISR) . . . . . . . . . . . . . . . . . 996
26.5.58 HRTIM output disable status register (HRTIM_ODSR) . . . . . . . . . . . . 997
26.5.59 HRTIM burst mode control register (HRTIM_BMCR) . . . . . . . . . . . . . 998
26.5.60 HRTIM burst mode trigger register (HRTIM_BMTRGR) . . . . . . . . . . 1000
26.5.61 HRTIM burst mode compare register (HRTIM_BMCMPR) . . . . . . . . 1002
26.5.62 HRTIM burst mode period register (HRTIM_BMPER) . . . . . . . . . . . . 1002
26.5.63 HRTIM timer external event control register 1 (HRTIM_EECR1) . . . 1003
26.5.64 HRTIM timer external event control register 2 (HRTIM_EECR2) . . . 1005
26.5.65 HRTIM timer external event control register 3 (HRTIM_EECR3) . . . 1006
26.5.66 HRTIM ADC trigger 1 register (HRTIM_ADC1R) . . . . . . . . . . . . . . . . 1007
26.5.67 HRTIM ADC trigger 2 register (HRTIM_ADC2R) . . . . . . . . . . . . . . . . 1008
26.5.68 HRTIM ADC trigger 3 register (HRTIM_ADC3R) . . . . . . . . . . . . . . . . 1009
26.5.69 HRTIM ADC trigger 4 register (HRTIM_ADC4R) . . . . . . . . . . . . . . . . 1011
26.5.70 HRTIM DLL control register (HRTIM_DLLCR) . . . . . . . . . . . . . . . . . . 1013
26.5.71 HRTIM fault input register 1 (HRTIM_FLTINR1) . . . . . . . . . . . . . . . . 1014
26.5.72 HRTIM fault input register 2 (HRTIM_FLTINR2) . . . . . . . . . . . . . . . . 1016
26.5.73 HRTIM burst DMA master timer update register (HRTIM_BDMUPR) 1018
26.5.74 HRTIM burst DMA timer x update register (HRTIM_BDTxUPR)
26.5.75 HRTIM burst DMA data register (HRTIM_BDMADR) . . . . . . . . . . . . 1020
24/2083
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
RM0440 Rev 1
RM0440