Figure 378. External Trigger Input Block - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
TIMx_AF1[17:14]
TIM_ETR
tim_etr_in
(tim_etr0)
tim_etr[1..15]
For example, to configure the upcounter to count each 2 rising edges on tim_etr_in, use the
following procedure:
1. Select the proper tim_etr_in source (internal or external) with the ETRSEL[3:0] bits in
the TIMx_AF1 register.
2. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
3. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
4. Select rising edge detection on the tim_etr_in by writing ETP=0 in the TIMx_SMCR
register
5. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 tim_etr_in rising edges.
The delay between the rising edge on tim_etr_in and the actual clock of the counter is due
to the resynchronization circuit on the tim_etrp signal. As a consequence, the maximum
frequency that can be correctly captured by the counter is at most ¼ of TIMxCLK frequency.
When the ETRP signal is faster, the user should apply a division of the external signal by a
proper ETPS prescaler setting.
1206/2083

Figure 378. External trigger input block

0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
or
tim_etrp
Filter
f downcounter
DTS
ETF[3:0]
TIMx_SMCR
RM0440 Rev 1
tim_ti1f or
Encoder
tim_ti2f or
mode
External clock
tim_trgi
mode 1
External clock
tim_etrf
mode 2
Internal clock
tim_ker_ck
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
RM0440
tim_psc_ck
MSv62385V1