Table 117. Nor Flash/Psram: Example Of Supported Memories And Transactions - ST STM32G4 Series Reference Manual

RM0440
FMC signal name I/O
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
18.5.2 Supported memories and transactions
Table 117
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.

Table 117. NOR Flash/PSRAM: example of supported memories and transactions

Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
Table 116. 16-Bit multiplexed I/O PSRAM (continued)
O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
O
O
O Address valid PSRAM input (memory signal name: NADV)
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
below shows an example of the supported devices, access modes and
Mode R/W
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Function
Output enable
Write enable
PSRAM wait input signal to the FMC
AHB
Memory
data
data size
size
R 8 16
W 8 16
R 16 16
W 16 16
R 32 16
W 32 16
R - 16
R 8 16
R 16 16
R 32 16
RM0440 Rev 1
Flexible memory controller (FMC)
Allowed/
not Comments
allowed
Y
N
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
N Mode is not supported
N
Y
Y
-
-
-
-
-
-
-
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