Table 318. Dma Channel Configuration For Aes-To-Memory Data Transfer; Figure 525. Dma Transfer Of A 128-Bit Data Block During Output Phase - ST STM32G4 Series Reference Manual

RM0440
Data output using DMA
Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The
AES peripheral then initiates a DMA request during the Output phase each time it requires
to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in

Table 318. DMA channel configuration for AES-to-memory data transfer

DMA channel control
register field
Transfer size
Source burst size
(peripheral)
Destination burst size
(memory)
DMA FIFIO size
Source transfer width
(peripheral)
Destination transfer
width (memory)
Source address
increment (peripheral)
Destination address
increment (memory)
Note: According to the message size, extra bytes might need to be discarded by application in the
last block.

Figure 525. DMA transfer of a 128-bit data block during output phase

Word3
DOUT[127:96]
D127
MSB
DMA
DMA req N
single read
1
(No swapping)
1
O127
MSB
1 4
Order of read from AES_DOUTR
It is the message length multiple of AES block size (4 words). According to
the case extra bytes will have to be discarded.
Single
Single
AES FIFO_size = 4 bytes
32-bit words
32-bit words
Fixed address of AES_DINR (no increment)
Yes, after each 32-bit transfer
Chronological order
Increasing address
Memory accessed through DMA
Word2
DOUT[95:64]
D96 D95
DMA
DMA req N+1
single read
2
2
AES core output buffer
O96 O95
Recommended configuration
Word1
DOUT[63:32]
D64 D63
DMA
DMA req N+2
single read
3
AES_DOUTR
3
O64 O63
RM0440 Rev 1
AES hardware accelerator (AES)
Word0
DOUT[31:0]
D32 D31
DMA
DMA req N+3
single read
4
4
O32 O31
Figure 525.
D0
LSB
O0
LSB
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