Table 132. Fmc_Bcrx Bit Fields; Figure 63. Muxed Write Access Waveforms - ST STM32G4 Series Reference Manual

RM0440
A[25:16]
NADV
NBL[x:0]
NEx
NOE
NWE
AD[15:0]
The difference with ModeD is the drive of the lower address byte(s) on the data bus.
Bit number
31:24
23:22
20
19
18:16
15
14
13
12
11
10
9
8
7
6

Figure 63. Muxed write access waveforms

Lower address
NBLSET ADDSET HCLK cycles
HCLK
cycles

Table 132. FMC_BCRx bit fields

Bit name
Reserved 0x000
NBLSET[1:0] As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x0
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
RM0440 Rev 1
Flexible memory controller (FMC)
Memory transaction
Data driven by controller
ADDHLD DATAST HCLK cycles
HCLK cycles
Value to set
DATAHLD +1
HCLK cycles
MSv41686V1
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