Table 386. Wwdg Register Map And Reset Values - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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System window watchdog (WWDG)

Status register (WWDG_SR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag

WWDG register map

The following table gives the WWDG register map and reset values.

This bit is set by hardware when the counter has reached the value 0x40. It must be cleared

by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not

Table 386. WWDG register map and reset values

Section 2.2 on page 78

for the register boundary addresses.

RM0440 Rev 1

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