ST STM32G4 Series Reference Manual page 524

Flexible memory controller (FMC)
To perform an ECC computation:
1. Enable the ECCEN bit in the FMC_PCR register.
2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC
block computes the ECC value.
3. Read the ECC value available in the FMC_ECCR register and store it in a variable.
4. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back
the written data from the NAND page. While the NAND page is read, the ECC block
computes the ECC value.
5. Read the new ECC value available in the FMC_ECCR register.
6. If the two ECC values are the same, no correction is required, otherwise there is an
ECC error and the software correction routine returns information on whether the error
can be corrected or not.
18.6.7 NAND Flash controller registers
NAND Flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018
31 30 29
Res. Res. Res. Res.
15 14 13
TAR[2:0]
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:17 ECCPS[2:0]: ECC page size.
Bits 16:13 TAR[3:0]: ALE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
524/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
TCLR[3:0]
rw rw rw rw
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. ECCEN
rw
RM0440 Rev 1
21 20 19 18
Res. ECCPS[2:0]
rw rw
5 4 3 2
PWID[1:0] PTYP PBKEN PWAITEN
rw rw rw rw
RM0440
17 16
TAR3
rw rw
1 0
Res.
rw