ST STM32G4 Series Reference Manual page 577

RM0440
20.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)
First of all, follow the procedure explained in
(DEEPPWD) and ADC voltage regulator
Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a
stabilization time of t
control bits enable or disable the ADC:
•
ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for
operation.
•
ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by
hardware as soon as the analog ADC is effectively disabled.
Regular conversion can then start either by setting ADSTART=1 (refer to
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL,
or when an external trigger event occurs, if triggers are enabled.
Injected conversions start by setting JADSTART=1 or when an external injected trigger
event occurs, if injected triggers are enabled.
Software procedure to enable the ADC
1. Clear the ADRDY bit in the ADC_ISR register by writing '1'.
2. Set ADEN=1.
3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done
using the associated interrupt (setting ADRDYIE=1).
4. Clear the ADRDY bit in the ADC_ISR register by writing '1' (optional).
Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the
ADCAL bit is cleared by hardware (end of the calibration).
Software procedure to disable the ADC
1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is
ongoing. If required, stop any regular and injected conversion ongoing by setting
ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively
disabled (ADDIS will automatically be reset once ADEN=0).
(ADVREGEN)).
before it starts converting accurately, as shown in
STAB
RM0440 Rev 1
Analog-to-digital converters (ADC)
Section 20.4.6: ADC Deep-power-down mode
Figure 89. Two
Section 20.4.18:
JEXTEN))
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