Flash Option Register (Flash_Optr) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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Embedded Flash memory (FLASH) for category 3 devices
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC: ECC fail address
3.7.8

Flash option register (FLASH_OPTR)

Address offset: 0x20
Reset value: 0xFXXX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31
30
29
NRST_MODE
Res.
IRHEN
[1:0]
rw
rw
15
14
13
nRST_
nRST_
nRST_
Res.
SHDW
STDBY
STOP
rw
rw
134/2083
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bit 21 BK_ECC: ECC fail bank
DBANK=1
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
DBANK=0
If SYSF_ECC is 1, it indicates which bank is concerned by the ECC error
If SYSF_ECC is 0, reserved, must be kept cleared.
DBANK=0
This bit indicates which address in the Flash memory is concerned by the ECC
error correction or by the double ECC error detection.
DBANK=1
This bit indicates which address in the bank is concerned by the ECC error
correction or by the double ECC error detection.
28
27
26
25
CCM
n
nSW
SRAM_
BOOT0
BOOT0
RST
rw
rw
rw
rw
12
11
10
9
Res.
BOR_LEV[2:0]
rw
rw
rw
24
23
22
SRAM
nBOOT
DBANK
_PE
1
rw
rw
rw
8
7
6
rw
rw
rw
RM0440 Rev 1
21
20
19
18
WWDG
IWGD_
Res.
BFB2
_SW
STDBY
rw
rw
rw
5
4
3
2
RDP[7:0]
rw
rw
rw
rw
RM0440
17
16
IWDG_
IWDG_
SW
StOP
rw
rw
1
0
rw
rw

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