ST STM32G4 Series Reference Manual page 305

Advanced arm-based 32-bit mcus

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CRS interrupt flag clear register (CRS_ICR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ESYNCC: Expected SYNC clear flag

Bit 2 ERRC: Error clear flag

Bit 1 SYNCWARNC: SYNC warning clear flag

Bit 0 SYNCOKC: SYNC event OK clear flag

Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.

Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also

the ERRF flag in the CRS_ISR register.

Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.

Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.

RM0440 Rev 1

Clock recovery system (CRS)

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