General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Figure 375. Control circuit in normal mode, internal clock divided by 1
tim_cnt_ck, tim_psc_ck
Counter register
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
TIMx_TISEL
TI2SEL[3:0]
TIM_CH2
tim_ti2_in0
tim_ti2
Filter
tim_ti2_in[1..15]
ICF[3:0]
TIMx_CCMR1
1. Codes ranging from 01000 to 11111: tim_itr[15..0].
For example, to configure the upcounter to count in response to a rising edge on the tim_ti2
input, use the following procedure:
For example, to configure the upcounter to count in response to a rising edge on the tim_ti2
input, use the following procedure:
1204/2083
tim_ker_ck
CEN
UG
CNT_INIT
31
Figure 376. tim_ti2 external clock connection example
tim_ti2f_rising
Edge
tim_ti2f_failing
detector
TIMx_CCER
3 2
33
34
35 36
TIMx_SMCR
TS[4:0]
or
tim_itrx
000xx
tim_ti1_ed
00100
tim_ti1fp1
00101
0
tim_ti2_fp2
00110
1
etrf
00111
(1)
CC2P
RM0440 Rev 1
00
01
02
03 04 05
tim_ti2f
or
Encoder
tim_ti1f
or
mode
External clock
tim_trgi
mode 1
External clock
tim_etrf
mode 2
Internal clock
tim_ker_ck
mode
(internal clock)
ECE
SMS[2:0]
TIMx_SMCR
RM0440
06
07
MSv62317V1
tim_psc_ck
MSv62318V1
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